rockchip: implement board_lmb_reserve()
Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". This makes lmb_alloc_base() always alloc from tail of sdram. If we don't assign it, bi_dram[0] is used by default and it may cause lmb_alloc_base() fail when bi_dram[0] range is small. Change-Id: I13c2c2d6135e26e647dcfde4c173d896c800fea5 Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
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@ -275,6 +275,47 @@ void enable_caches(void)
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dcache_enable();
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dcache_enable();
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}
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}
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/*
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* Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize".
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* This makes lmb_alloc_base() always alloc from tail of sdram.
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* If we don't assign it, bi_dram[0] is used by default and it may cause
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* lmb_alloc_base() fail when bi_dram[0] range is small.
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*/
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void board_lmb_reserve(struct lmb *lmb)
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{
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u64 start, size;
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char bootm_low[32];
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char bootm_mapsize[32];
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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if (!gd->bd->bi_dram[i].size)
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break;
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}
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start = gd->bd->bi_dram[i - 1].start;
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size = gd->bd->bi_dram[i - 1].size;
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/*
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* 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area, otherwise
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* "Unable to handle kernel paging request at virtual address ...".
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* If so, using low address region, i.e before tustos region(132MB).
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*/
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#ifndef ARM64
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if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_768M)) {
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start = gd->bd->bi_dram[i - 2].start;
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size = gd->bd->bi_dram[i - 2].size;
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}
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if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_768M))
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size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_768M - start;
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#endif
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sprintf(bootm_low, "0x%llx", start);
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sprintf(bootm_mapsize, "0x%llx", size);
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env_set("bootm_low", bootm_low);
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env_set("bootm_mapsize", bootm_mapsize);
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}
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#ifdef CONFIG_ROCKCHIP_PRELOADER_SERIAL
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#ifdef CONFIG_ROCKCHIP_PRELOADER_SERIAL
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int board_init_f_init_serial(void)
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int board_init_f_init_serial(void)
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{
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{
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@ -40,6 +40,7 @@
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#define SZ_128M 0x08000000
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#define SZ_128M 0x08000000
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#define SZ_256M 0x10000000
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#define SZ_256M 0x10000000
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#define SZ_512M 0x20000000
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#define SZ_512M 0x20000000
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#define SZ_768M 0x30000000
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#define SZ_1G 0x40000000
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#define SZ_1G 0x40000000
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#define SZ_2G 0x80000000
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#define SZ_2G 0x80000000
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