rockchip: dts: rk3568: Resync from kernel-4.19
Resync from kernel-4.19: (2f153f1fa73c arm64: dts: rockchip: rk3568: add thermal-zone for pvtm) Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I36fdfc366f4d44f3226b6f8b35ee496701fe021e
This commit is contained in:
Joseph Chen
Jianhong Chen
parent
6a71ec51e6
commit
2d25c32e07
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@ -30,39 +30,24 @@
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<1 RK_PA5 5 &pcfg_pull_none>;
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};
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};
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audiopwmlout {
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audiopwmlout_pins: audiopwmlout-pins {
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audiopwmout {
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audiopwmout_pins: audiopwmout-pins {
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rockchip,pins =
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/* audiopwmlout */
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<1 RK_PA0 4 &pcfg_pull_none>,
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/* audiopwmlout */
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<1 RK_PA1 6 &pcfg_pull_none>;
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};
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};
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audiopwmloutp {
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audiopwmloutp_pins: audiopwmloutp-pins {
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rockchip,pins =
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/* audiopwmloutp */
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<1 RK_PA0 6 &pcfg_pull_none>;
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};
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};
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audiopwmrout {
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audiopwmrout_pins: audiopwmrout-pins {
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rockchip,pins =
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/* audiopwmrout */
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<1 RK_PA1 4 &pcfg_pull_none>;
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};
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};
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audiopwmroutn {
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audiopwmroutn_pins: audiopwmroutn-pins {
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audiopwmoutdiff {
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audiopwmoutdiff_pins: audiopwmoutdiff-pins {
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rockchip,pins =
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/* audiopwmloutn */
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<1 RK_PA1 6 &pcfg_pull_none>,
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/* audiopwmloutp */
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<1 RK_PA0 6 &pcfg_pull_none>,
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/* audiopwmroutn */
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<1 RK_PA7 4 &pcfg_pull_none>;
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};
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};
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audiopwmroutp {
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audiopwmroutp_pins: audiopwmroutp-pins {
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rockchip,pins =
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<1 RK_PA7 4 &pcfg_pull_none>,
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/* audiopwmroutp */
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<1 RK_PA6 4 &pcfg_pull_none>;
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};
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@ -384,19 +369,19 @@
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};
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};
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eth0 {
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eth0_pins: eth0-pins {
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eth0_clkout_pins: eth0-clkout-pins {
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rockchip,pins =
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/* eth0_refclko25m */
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<2 RK_PC1 2 &pcfg_pull_none>;
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};
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};
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eth1 {
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eth1m0_pins: eth1m0-pins {
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eth1m0_clkout_pins: eth1m0-clkout-pins {
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rockchip,pins =
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/* eth1_refclko25mm0 */
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<3 RK_PB0 3 &pcfg_pull_none>;
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};
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eth1m1_pins: eth1m1-pins {
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eth1m1_clkout_pins: eth1m1-clkout-pins {
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rockchip,pins =
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/* eth1_refclko25mm1 */
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<4 RK_PB3 3 &pcfg_pull_none>;
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@ -466,14 +451,34 @@
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};
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};
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gmac0 {
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gmac0_pins: gmac0-pins {
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gmac0_miim_pins: gmac0-miim-pins {
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rockchip,pins =
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/* gmac0_mclkinout */
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<2 RK_PC2 2 &pcfg_pull_none>,
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/* gmac0_mdc */
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<2 RK_PC3 2 &pcfg_pull_none>,
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/* gmac0_mdio */
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<2 RK_PC4 2 &pcfg_pull_none>,
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<2 RK_PC4 2 &pcfg_pull_none>;
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};
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gmac0_rmii_pins: gmac0-rmii-pins {
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rockchip,pins =
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/* gmac0_mclkinout */
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<2 RK_PC2 2 &pcfg_pull_none>,
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/* gmac0_rxd0 */
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<2 RK_PB6 1 &pcfg_pull_none>,
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/* gmac0_rxd1 */
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<2 RK_PB7 2 &pcfg_pull_none>,
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/* gmac0_rxdvcrs */
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<2 RK_PC0 2 &pcfg_pull_none>,
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/* gmac0_rxer */
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<2 RK_PC5 2 &pcfg_pull_none>,
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/* gmac0_txd0 */
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<2 RK_PB3 1 &pcfg_pull_none>,
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/* gmac0_txd1 */
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<2 RK_PB4 1 &pcfg_pull_none>,
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/* gmac0_txen */
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<2 RK_PB5 1 &pcfg_pull_none>;
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};
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gmac0_rgmii_pins: gmac0-rgmii-pins {
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rockchip,pins =
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/* gmac0_rxclk */
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<2 RK_PA5 2 &pcfg_pull_none>,
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/* gmac0_rxd0 */
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@ -486,31 +491,49 @@
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<2 RK_PA4 2 &pcfg_pull_none>,
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/* gmac0_rxdvcrs */
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<2 RK_PC0 2 &pcfg_pull_none>,
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/* gmac0_rxer */
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<2 RK_PC5 2 &pcfg_pull_none>,
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/* gmac0_txclk */
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<2 RK_PB0 2 &pcfg_pull_none>,
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<2 RK_PB0 2 &pcfg_pull_none_drv_level_15>,
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/* gmac0_txd0 */
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<2 RK_PB3 1 &pcfg_pull_none>,
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<2 RK_PB3 1 &pcfg_pull_none_drv_level_15>,
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/* gmac0_txd1 */
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<2 RK_PB4 1 &pcfg_pull_none>,
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<2 RK_PB4 1 &pcfg_pull_none_drv_level_15>,
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/* gmac0_txd2 */
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<2 RK_PA6 2 &pcfg_pull_none>,
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<2 RK_PA6 2 &pcfg_pull_none_drv_level_15>,
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/* gmac0_txd3 */
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<2 RK_PA7 2 &pcfg_pull_none>,
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<2 RK_PA7 2 &pcfg_pull_none_drv_level_15>,
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/* gmac0_txen */
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<2 RK_PB5 1 &pcfg_pull_none>;
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};
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};
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gmac1 {
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gmac1m0_pins: gmac1m0-pins {
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gmac1m0_miim_pins: gmac1m0-miim-pins {
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rockchip,pins =
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/* gmac1_mclkinoutm0 */
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<3 RK_PC0 3 &pcfg_pull_none>,
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/* gmac1_mdcm0 */
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<3 RK_PC4 3 &pcfg_pull_none>,
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/* gmac1_mdiom0 */
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<3 RK_PC5 3 &pcfg_pull_none>,
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<3 RK_PC5 3 &pcfg_pull_none>;
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};
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gmac1m0_rmii_pins: gmac1m0-rmii-pins {
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rockchip,pins =
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/* gmac1_mclkinoutm0 */
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<3 RK_PC0 3 &pcfg_pull_none>,
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/* gmac1_rxd0m0 */
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<3 RK_PB1 3 &pcfg_pull_none>,
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/* gmac1_rxd1m0 */
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<3 RK_PB2 3 &pcfg_pull_none>,
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/* gmac1_rxdvcrsm0 */
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<3 RK_PB3 3 &pcfg_pull_none>,
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/* gmac1_rxerm0 */
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<3 RK_PB4 3 &pcfg_pull_none>,
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/* gmac1_txd0m0 */
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<3 RK_PB5 3 &pcfg_pull_none>,
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/* gmac1_txd1m0 */
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<3 RK_PB6 3 &pcfg_pull_none>,
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/* gmac1_txenm0 */
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<3 RK_PB7 3 &pcfg_pull_none>;
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};
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gmac1m0_rgmii_pins: gmac1m0-rgmii-pins {
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rockchip,pins =
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/* gmac1_rxclkm0 */
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<3 RK_PA7 3 &pcfg_pull_none>,
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/* gmac1_rxd0m0 */
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@ -523,29 +546,47 @@
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<3 RK_PA5 3 &pcfg_pull_none>,
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/* gmac1_rxdvcrsm0 */
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<3 RK_PB3 3 &pcfg_pull_none>,
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/* gmac1_rxerm0 */
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<3 RK_PB4 3 &pcfg_pull_none>,
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/* gmac1_txclkm0 */
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<3 RK_PA6 3 &pcfg_pull_none>,
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<3 RK_PA6 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txd0m0 */
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<3 RK_PB5 3 &pcfg_pull_none>,
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<3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txd1m0 */
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<3 RK_PB6 3 &pcfg_pull_none>,
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<3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txd2m0 */
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<3 RK_PA2 3 &pcfg_pull_none>,
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<3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txd3m0 */
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<3 RK_PA3 3 &pcfg_pull_none>,
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<3 RK_PA3 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txenm0 */
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<3 RK_PB7 3 &pcfg_pull_none>;
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};
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gmac1m1_pins: gmac1m1-pins {
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gmac1m1_miim_pins: gmac1m1-miim-pins {
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rockchip,pins =
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/* gmac1_mclkinoutm1 */
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<4 RK_PC1 3 &pcfg_pull_none>,
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/* gmac1_mdcm1 */
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<4 RK_PB6 3 &pcfg_pull_none>,
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/* gmac1_mdiom1 */
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<4 RK_PB7 3 &pcfg_pull_none>,
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<4 RK_PB7 3 &pcfg_pull_none>;
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};
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gmac1m1_rmii_pins: gmac1m1-rmii-pins {
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rockchip,pins =
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/* gmac1_mclkinoutm1 */
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<4 RK_PC1 3 &pcfg_pull_none>,
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/* gmac1_rxd0m1 */
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<4 RK_PA7 3 &pcfg_pull_none>,
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/* gmac1_rxd1m1 */
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<4 RK_PB0 3 &pcfg_pull_none>,
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/* gmac1_rxdvcrsm1 */
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<4 RK_PB1 3 &pcfg_pull_none>,
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/* gmac1_rxerm1 */
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<4 RK_PB2 3 &pcfg_pull_none>,
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/* gmac1_txd0m1 */
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<4 RK_PA4 3 &pcfg_pull_none>,
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/* gmac1_txd1m1 */
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<4 RK_PA5 3 &pcfg_pull_none>,
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/* gmac1_txenm1 */
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<4 RK_PA6 3 &pcfg_pull_none>;
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};
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gmac1m1_rgmii_pins: gmac1m1-rgmii-pins {
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rockchip,pins =
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/* gmac1_rxclkm1 */
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<4 RK_PA3 3 &pcfg_pull_none>,
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/* gmac1_rxd0m1 */
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@ -558,18 +599,16 @@
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<4 RK_PA2 3 &pcfg_pull_none>,
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/* gmac1_rxdvcrsm1 */
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<4 RK_PB1 3 &pcfg_pull_none>,
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/* gmac1_rxerm1 */
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<4 RK_PB2 3 &pcfg_pull_none>,
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/* gmac1_txclkm1 */
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<4 RK_PA0 3 &pcfg_pull_none>,
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<4 RK_PA0 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txd0m1 */
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<4 RK_PA4 3 &pcfg_pull_none>,
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<4 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txd1m1 */
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<4 RK_PA5 3 &pcfg_pull_none>,
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<4 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txd2m1 */
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<3 RK_PD6 3 &pcfg_pull_none>,
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<3 RK_PD6 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txd3m1 */
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<3 RK_PD7 3 &pcfg_pull_none>,
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<3 RK_PD7 3 &pcfg_pull_none_drv_level_15>,
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/* gmac1_txenm1 */
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<4 RK_PA6 3 &pcfg_pull_none>;
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};
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@ -584,12 +623,12 @@
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};
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};
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hdmitx {
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hdmitxm0_pins: hdmitxm0-pins {
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hdmitxm0_cec: hdmitxm0-cec {
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rockchip,pins =
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/* hdmitx_cecm0 */
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<4 RK_PD1 1 &pcfg_pull_none>;
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};
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hdmitxm1_pins: hdmitxm1-pins {
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hdmitxm1_cec: hdmitxm1-cec {
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rockchip,pins =
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/* hdmitx_cecm1 */
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<0 RK_PC7 1 &pcfg_pull_none>;
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@ -1475,7 +1514,7 @@
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sdmmc0_clk: sdmmc0-clk {
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rockchip,pins =
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/* sdmmc0_clk */
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<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
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<2 RK_PA2 1 &pcfg_pull_up_drv_level_1>;
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};
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sdmmc0_cmd: sdmmc0-cmd {
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rockchip,pins =
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@ -1495,23 +1534,23 @@
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sdmmc1_bus4: sdmmc1-bus4 {
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rockchip,pins =
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/* sdmmc1_d0 */
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<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
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<2 RK_PA3 1 &pcfg_pull_up_drv_level_5>,
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/* sdmmc1_d1 */
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<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
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<2 RK_PA4 1 &pcfg_pull_up_drv_level_5>,
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/* sdmmc1_d2 */
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<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
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<2 RK_PA5 1 &pcfg_pull_up_drv_level_5>,
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/* sdmmc1_d3 */
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<2 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
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<2 RK_PA6 1 &pcfg_pull_up_drv_level_5>;
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};
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sdmmc1_clk: sdmmc1-clk {
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rockchip,pins =
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/* sdmmc1_clk */
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<2 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
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<2 RK_PB0 1 &pcfg_pull_up_drv_level_5>;
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};
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sdmmc1_cmd: sdmmc1-cmd {
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rockchip,pins =
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/* sdmmc1_cmd */
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<2 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
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<2 RK_PA7 1 &pcfg_pull_up_drv_level_5>;
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};
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sdmmc1_det: sdmmc1-det {
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rockchip,pins =
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@ -1526,23 +1565,23 @@
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sdmmc2m0_bus4: sdmmc2m0-bus4 {
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rockchip,pins =
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/* sdmmc2_d0m0 */
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<3 RK_PC6 3 &pcfg_pull_up_drv_level_2>,
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<3 RK_PC6 3 &pcfg_pull_up_drv_level_5>,
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/* sdmmc2_d1m0 */
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<3 RK_PC7 3 &pcfg_pull_up_drv_level_2>,
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<3 RK_PC7 3 &pcfg_pull_up_drv_level_5>,
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/* sdmmc2_d2m0 */
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<3 RK_PD0 3 &pcfg_pull_up_drv_level_2>,
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<3 RK_PD0 3 &pcfg_pull_up_drv_level_5>,
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/* sdmmc2_d3m0 */
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<3 RK_PD1 3 &pcfg_pull_up_drv_level_2>;
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<3 RK_PD1 3 &pcfg_pull_up_drv_level_5>;
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};
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sdmmc2m0_clk: sdmmc2m0-clk {
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rockchip,pins =
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/* sdmmc2_clkm0 */
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<3 RK_PD3 3 &pcfg_pull_up_drv_level_2>;
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<3 RK_PD3 3 &pcfg_pull_up_drv_level_5>;
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};
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sdmmc2m0_cmd: sdmmc2m0-cmd {
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rockchip,pins =
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/* sdmmc2_cmdm0 */
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<3 RK_PD2 3 &pcfg_pull_up_drv_level_2>;
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<3 RK_PD2 3 &pcfg_pull_up_drv_level_5>;
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};
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sdmmc2detm0: sdmmc2detm0 {
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rockchip,pins =
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@ -1555,23 +1594,23 @@
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sdmmc2m1_bus4: sdmmc2m1-bus4 {
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rockchip,pins =
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/* sdmmc2_d0m1 */
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<3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
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<3 RK_PA1 5 &pcfg_pull_up_drv_level_5>,
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/* sdmmc2_d1m1 */
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<3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
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<3 RK_PA2 5 &pcfg_pull_up_drv_level_5>,
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/* sdmmc2_d2m1 */
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<3 RK_PA3 5 &pcfg_pull_up_drv_level_2>,
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<3 RK_PA3 5 &pcfg_pull_up_drv_level_5>,
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/* sdmmc2_d3m1 */
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<3 RK_PA4 5 &pcfg_pull_up_drv_level_2>;
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<3 RK_PA4 5 &pcfg_pull_up_drv_level_5>;
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};
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sdmmc2m1_clk: sdmmc2m1-clk {
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rockchip,pins =
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/* sdmmc2_clkm1 */
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<3 RK_PA6 5 &pcfg_pull_up_drv_level_2>;
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<3 RK_PA6 5 &pcfg_pull_up_drv_level_5>;
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};
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sdmmc2m1_cmd: sdmmc2m1-cmd {
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rockchip,pins =
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/* sdmmc2_cmdm1 */
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<3 RK_PA5 5 &pcfg_pull_up_drv_level_2>;
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<3 RK_PA5 5 &pcfg_pull_up_drv_level_5>;
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};
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sdmmc2detm1: sdmmc2detm1 {
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rockchip,pins =
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@ -1620,6 +1659,18 @@
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rockchip,pins =
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<0 RK_PB6 2 &pcfg_pull_none>;
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};
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spi0clkm0_hs: spi0clkm0-hs {
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rockchip,pins =
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<0 RK_PB5 2 &pcfg_pull_up_drv_level_1>;
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};
|
||||
spi0misom0_hs: spi0misom0-hs {
|
||||
rockchip,pins =
|
||||
<0 RK_PC5 2 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi0mosim0_hs: spi0mosim0-hs {
|
||||
rockchip,pins =
|
||||
<0 RK_PB6 2 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi0clkm1: spi0clkm1 {
|
||||
rockchip,pins =
|
||||
<2 RK_PD3 3 &pcfg_pull_none>;
|
||||
|
|
@ -1636,6 +1687,18 @@
|
|||
rockchip,pins =
|
||||
<2 RK_PD1 3 &pcfg_pull_none>;
|
||||
};
|
||||
spi0clkm1_hs: spi0clkm1-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PD3 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi0misom1_hs: spi0misom1-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PD0 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi0mosim1_hs: spi0mosim1-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PD1 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
};
|
||||
spi1 {
|
||||
spi1clkm0: spi1clkm0 {
|
||||
|
|
@ -1658,6 +1721,18 @@
|
|||
rockchip,pins =
|
||||
<2 RK_PB7 4 &pcfg_pull_none>;
|
||||
};
|
||||
spi1clkm0_hs: spi1clkm0-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PB5 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi1misom0_hs: spi1misom0-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PB6 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi1mosim0_hs: spi1mosim0-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PB7 4 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi1clkm1: spi1clkm1 {
|
||||
rockchip,pins =
|
||||
<3 RK_PC3 3 &pcfg_pull_none>;
|
||||
|
|
@ -1674,6 +1749,18 @@
|
|||
rockchip,pins =
|
||||
<3 RK_PC1 3 &pcfg_pull_none>;
|
||||
};
|
||||
spi1clkm1_hs: spi1clkm1-hs {
|
||||
rockchip,pins =
|
||||
<3 RK_PC3 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi1misom1_hs: spi1misom1-hs {
|
||||
rockchip,pins =
|
||||
<3 RK_PC2 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi1mosim1_hs: spi1mosim1-hs {
|
||||
rockchip,pins =
|
||||
<3 RK_PC1 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
};
|
||||
spi2 {
|
||||
spi2clkm0: spi2clkm0 {
|
||||
|
|
@ -1696,6 +1783,18 @@
|
|||
rockchip,pins =
|
||||
<2 RK_PC3 4 &pcfg_pull_none>;
|
||||
};
|
||||
spi2clkm0_hs: spi2clkm0-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PC1 4 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi2misom0_hs: spi2misom0-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PC2 4 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi2mosim0_hs: spi2mosim0-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PC3 4 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi2clkm1: spi2clkm1 {
|
||||
rockchip,pins =
|
||||
<3 RK_PA0 3 &pcfg_pull_none>;
|
||||
|
|
@ -1716,6 +1815,18 @@
|
|||
rockchip,pins =
|
||||
<2 RK_PD6 3 &pcfg_pull_none>;
|
||||
};
|
||||
spi2clkm1_hs: spi2clkm1-hs {
|
||||
rockchip,pins =
|
||||
<3 RK_PA0 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi2misom1_hs: spi2misom1-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PD7 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi2mosim1_hs: spi2mosim1-hs {
|
||||
rockchip,pins =
|
||||
<2 RK_PD6 3 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
};
|
||||
spi3 {
|
||||
spi3clkm0: spi3clkm0 {
|
||||
|
|
@ -1738,6 +1849,18 @@
|
|||
rockchip,pins =
|
||||
<4 RK_PB2 4 &pcfg_pull_none>;
|
||||
};
|
||||
spi3clkm0_hs: spi3clkm0-hs {
|
||||
rockchip,pins =
|
||||
<4 RK_PB3 4 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi3misom0_hs: spi3misom0-hs {
|
||||
rockchip,pins =
|
||||
<4 RK_PB0 4 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi3mosim0_hs: spi3mosim0-hs {
|
||||
rockchip,pins =
|
||||
<4 RK_PB2 4 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi3clkm1: spi3clkm1 {
|
||||
rockchip,pins =
|
||||
<4 RK_PC2 2 &pcfg_pull_none>;
|
||||
|
|
@ -1758,8 +1881,23 @@
|
|||
rockchip,pins =
|
||||
<4 RK_PC3 2 &pcfg_pull_none>;
|
||||
};
|
||||
spi3clkm1_hs: spi3clkm1-hs {
|
||||
rockchip,pins =
|
||||
<4 RK_PC2 2 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi3misom1_hs: spi3misom1-hs {
|
||||
rockchip,pins =
|
||||
<4 RK_PC5 2 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
spi3mosim1_hs: spi3mosim1-hs {
|
||||
rockchip,pins =
|
||||
<4 RK_PC3 2 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
};
|
||||
tsadc {
|
||||
tsadc_gpio: tsadc-gpio {
|
||||
rockchip,pins = <0 RK_PA1 0 &pcfg_pull_none>;
|
||||
};
|
||||
tsadcm0_pins: tsadcm0-pins {
|
||||
rockchip,pins =
|
||||
/* tsadc_shutm0 */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -59,8 +59,10 @@
|
|||
#define PCLK_GPIO0 46
|
||||
#define PCLK_PMUPVTM 47
|
||||
#define PCLK_PWM0 48
|
||||
#define CLK_PDPMU 49
|
||||
#define SCLK_32K_IOE 50
|
||||
|
||||
#define CLKPMU_NR_CLKS (PCLK_PWM0 + 1)
|
||||
#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1)
|
||||
|
||||
/* cru-clocks indices */
|
||||
|
||||
|
|
@ -290,7 +292,6 @@
|
|||
#define PCLK_HDCP 229
|
||||
#define PCLK_HDMI_HOST 230
|
||||
#define CLK_HDMI_SFR 231
|
||||
#define CLK_HDMI_CEC 231
|
||||
#define PCLK_DSITX_0 232
|
||||
#define PCLK_DSITX_1 233
|
||||
#define PCLK_EDP_CTRL 234
|
||||
|
|
@ -462,7 +463,15 @@
|
|||
#define SCLK_EMMC_DRV 400
|
||||
#define SCLK_EMMC_SAMPLE 401
|
||||
#define PCLK_EDPPHY_GRF 402
|
||||
#define PCLK_CORE_PVTM 403
|
||||
#define CLK_HDMI_CEC 403
|
||||
#define CLK_I2S0_8CH_TX 404
|
||||
#define CLK_I2S0_8CH_RX 405
|
||||
#define CLK_I2S1_8CH_TX 406
|
||||
#define CLK_I2S1_8CH_RX 407
|
||||
#define CLK_I2S2_2CH 408
|
||||
#define CLK_I2S3_2CH_TX 409
|
||||
#define CLK_I2S3_2CH_RX 410
|
||||
#define PCLK_CORE_PVTM 450
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
|
||||
|
||||
|
|
@ -623,12 +632,42 @@
|
|||
|
||||
/* cru_softrst_con10 */
|
||||
#define SRST_P_PCIE20 160
|
||||
#define SRST_PCIE20_POWERUP 161
|
||||
#define SRST_MSTR_ARESET_PCIE20 162
|
||||
#define SRST_SLV_ARESET_PCIE20 163
|
||||
#define SRST_DBI_ARESET_PCIE20 164
|
||||
#define SRST_BRESET_PCIE20 165
|
||||
#define SRST_PERST_PCIE20 166
|
||||
#define SRST_CORE_RST_PCIE20 167
|
||||
#define SRST_NSTICKY_RST_PCIE20 168
|
||||
#define SRST_STICKY_RST_PCIE20 169
|
||||
#define SRST_PWR_RST_PCIE20 170
|
||||
|
||||
/* cru_softrst_con11 */
|
||||
#define SRST_P_PCIE30X1 176
|
||||
#define SRST_PCIE30X1_POWERUP 177
|
||||
#define SRST_M_ARESET_PCIE30X1 178
|
||||
#define SRST_S_ARESET_PCIE30X1 179
|
||||
#define SRST_D_ARESET_PCIE30X1 180
|
||||
#define SRST_BRESET_PCIE30X1 181
|
||||
#define SRST_PERST_PCIE30X1 182
|
||||
#define SRST_CORE_RST_PCIE30X1 183
|
||||
#define SRST_NSTC_RST_PCIE30X1 184
|
||||
#define SRST_STC_RST_PCIE30X1 185
|
||||
#define SRST_PWR_RST_PCIE30X1 186
|
||||
|
||||
/* cru_softrst_con12 */
|
||||
#define SRST_P_PCIE30X2 192
|
||||
#define SRST_PCIE30X2_POWERUP 193
|
||||
#define SRST_M_ARESET_PCIE30X2 194
|
||||
#define SRST_S_ARESET_PCIE30X2 195
|
||||
#define SRST_D_ARESET_PCIE30X2 196
|
||||
#define SRST_BRESET_PCIE30X2 197
|
||||
#define SRST_PERST_PCIE30X2 198
|
||||
#define SRST_CORE_RST_PCIE30X2 199
|
||||
#define SRST_NSTC_RST_PCIE30X2 200
|
||||
#define SRST_STC_RST_PCIE30X2 201
|
||||
#define SRST_PWR_RST_PCIE30X2 202
|
||||
|
||||
/* cru_softrst_con13 */
|
||||
#define SRST_A_PHP_NIU 208
|
||||
|
|
|
|||
|
|
@ -15,5 +15,6 @@
|
|||
#define PHY_TYPE_PCIE 2
|
||||
#define PHY_TYPE_USB2 3
|
||||
#define PHY_TYPE_USB3 4
|
||||
#define PHY_TYPE_UFS 5
|
||||
|
||||
#endif /* _DT_BINDINGS_PHY */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ROCKCHIP_BOOT_MODE_H
|
||||
#define __ROCKCHIP_BOOT_MODE_H
|
||||
|
||||
/* high 24 bits is tag, low 8 bits is type */
|
||||
/*high 24 bits is tag, low 8 bits is type*/
|
||||
#define REBOOT_FLAG 0x5242C300
|
||||
/* normal boot */
|
||||
#define BOOT_NORMAL (REBOOT_FLAG + 0)
|
||||
|
|
@ -9,6 +10,10 @@
|
|||
#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1)
|
||||
/* enter recovery */
|
||||
#define BOOT_RECOVERY (REBOOT_FLAG + 3)
|
||||
/* reboot by panic */
|
||||
#define BOOT_PANIC (REBOOT_FLAG + 7)
|
||||
/* reboot by watchdog */
|
||||
#define BOOT_WATCHDOG (REBOOT_FLAG + 8)
|
||||
/* enter fastboot mode */
|
||||
#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
|
||||
/* enter charging mode */
|
||||
|
|
|
|||
Loading…
Reference in New Issue