From 2d25c32e077904ed34e65f00257be2f5d360d141 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 18 Nov 2020 16:25:45 +0800 Subject: [PATCH] rockchip: dts: rk3568: Resync from kernel-4.19 Resync from kernel-4.19: (2f153f1fa73c arm64: dts: rockchip: rk3568: add thermal-zone for pvtm) Signed-off-by: Joseph Chen Change-Id: I36fdfc366f4d44f3226b6f8b35ee496701fe021e --- arch/arm/dts/rk3568-pinctrl.dtsi | 300 +++- arch/arm/dts/rk3568.dtsi | 1385 +++++++++++++++++- include/dt-bindings/clock/rk3568-cru.h | 45 +- include/dt-bindings/phy/phy.h | 1 + include/dt-bindings/soc/rockchip,boot-mode.h | 7 +- 5 files changed, 1615 insertions(+), 123 deletions(-) diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi index 86009ff44e..427e5d1443 100644 --- a/arch/arm/dts/rk3568-pinctrl.dtsi +++ b/arch/arm/dts/rk3568-pinctrl.dtsi @@ -30,39 +30,24 @@ <1 RK_PA5 5 &pcfg_pull_none>; }; }; - audiopwmlout { - audiopwmlout_pins: audiopwmlout-pins { + audiopwmout { + audiopwmout_pins: audiopwmout-pins { rockchip,pins = /* audiopwmlout */ <1 RK_PA0 4 &pcfg_pull_none>, - /* audiopwmlout */ - <1 RK_PA1 6 &pcfg_pull_none>; - }; - }; - audiopwmloutp { - audiopwmloutp_pins: audiopwmloutp-pins { - rockchip,pins = - /* audiopwmloutp */ - <1 RK_PA0 6 &pcfg_pull_none>; - }; - }; - audiopwmrout { - audiopwmrout_pins: audiopwmrout-pins { - rockchip,pins = /* audiopwmrout */ <1 RK_PA1 4 &pcfg_pull_none>; }; }; - audiopwmroutn { - audiopwmroutn_pins: audiopwmroutn-pins { + audiopwmoutdiff { + audiopwmoutdiff_pins: audiopwmoutdiff-pins { rockchip,pins = + /* audiopwmloutn */ + <1 RK_PA1 6 &pcfg_pull_none>, + /* audiopwmloutp */ + <1 RK_PA0 6 &pcfg_pull_none>, /* audiopwmroutn */ - <1 RK_PA7 4 &pcfg_pull_none>; - }; - }; - audiopwmroutp { - audiopwmroutp_pins: audiopwmroutp-pins { - rockchip,pins = + <1 RK_PA7 4 &pcfg_pull_none>, /* audiopwmroutp */ <1 RK_PA6 4 &pcfg_pull_none>; }; @@ -384,19 +369,19 @@ }; }; eth0 { - eth0_pins: eth0-pins { + eth0_clkout_pins: eth0-clkout-pins { rockchip,pins = /* eth0_refclko25m */ <2 RK_PC1 2 &pcfg_pull_none>; }; }; eth1 { - eth1m0_pins: eth1m0-pins { + eth1m0_clkout_pins: eth1m0-clkout-pins { rockchip,pins = /* eth1_refclko25mm0 */ <3 RK_PB0 3 &pcfg_pull_none>; }; - eth1m1_pins: eth1m1-pins { + eth1m1_clkout_pins: eth1m1-clkout-pins { rockchip,pins = /* eth1_refclko25mm1 */ <4 RK_PB3 3 &pcfg_pull_none>; @@ -466,14 +451,34 @@ }; }; gmac0 { - gmac0_pins: gmac0-pins { + gmac0_miim_pins: gmac0-miim-pins { rockchip,pins = - /* gmac0_mclkinout */ - <2 RK_PC2 2 &pcfg_pull_none>, /* gmac0_mdc */ <2 RK_PC3 2 &pcfg_pull_none>, /* gmac0_mdio */ - <2 RK_PC4 2 &pcfg_pull_none>, + <2 RK_PC4 2 &pcfg_pull_none>; + }; + gmac0_rmii_pins: gmac0-rmii-pins { + rockchip,pins = + /* gmac0_mclkinout */ + <2 RK_PC2 2 &pcfg_pull_none>, + /* gmac0_rxd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* gmac0_rxdvcrs */ + <2 RK_PC0 2 &pcfg_pull_none>, + /* gmac0_rxer */ + <2 RK_PC5 2 &pcfg_pull_none>, + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + gmac0_rgmii_pins: gmac0-rgmii-pins { + rockchip,pins = /* gmac0_rxclk */ <2 RK_PA5 2 &pcfg_pull_none>, /* gmac0_rxd0 */ @@ -486,31 +491,49 @@ <2 RK_PA4 2 &pcfg_pull_none>, /* gmac0_rxdvcrs */ <2 RK_PC0 2 &pcfg_pull_none>, - /* gmac0_rxer */ - <2 RK_PC5 2 &pcfg_pull_none>, /* gmac0_txclk */ - <2 RK_PB0 2 &pcfg_pull_none>, + <2 RK_PB0 2 &pcfg_pull_none_drv_level_15>, /* gmac0_txd0 */ - <2 RK_PB3 1 &pcfg_pull_none>, + <2 RK_PB3 1 &pcfg_pull_none_drv_level_15>, /* gmac0_txd1 */ - <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none_drv_level_15>, /* gmac0_txd2 */ - <2 RK_PA6 2 &pcfg_pull_none>, + <2 RK_PA6 2 &pcfg_pull_none_drv_level_15>, /* gmac0_txd3 */ - <2 RK_PA7 2 &pcfg_pull_none>, + <2 RK_PA7 2 &pcfg_pull_none_drv_level_15>, /* gmac0_txen */ <2 RK_PB5 1 &pcfg_pull_none>; }; }; gmac1 { - gmac1m0_pins: gmac1m0-pins { + gmac1m0_miim_pins: gmac1m0-miim-pins { rockchip,pins = - /* gmac1_mclkinoutm0 */ - <3 RK_PC0 3 &pcfg_pull_none>, /* gmac1_mdcm0 */ <3 RK_PC4 3 &pcfg_pull_none>, /* gmac1_mdiom0 */ - <3 RK_PC5 3 &pcfg_pull_none>, + <3 RK_PC5 3 &pcfg_pull_none>; + }; + gmac1m0_rmii_pins: gmac1m0-rmii-pins { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none>, + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none>, + /* gmac1_rxerm0 */ + <3 RK_PB4 3 &pcfg_pull_none>, + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + gmac1m0_rgmii_pins: gmac1m0-rgmii-pins { + rockchip,pins = /* gmac1_rxclkm0 */ <3 RK_PA7 3 &pcfg_pull_none>, /* gmac1_rxd0m0 */ @@ -523,29 +546,47 @@ <3 RK_PA5 3 &pcfg_pull_none>, /* gmac1_rxdvcrsm0 */ <3 RK_PB3 3 &pcfg_pull_none>, - /* gmac1_rxerm0 */ - <3 RK_PB4 3 &pcfg_pull_none>, /* gmac1_txclkm0 */ - <3 RK_PA6 3 &pcfg_pull_none>, + <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txd0m0 */ - <3 RK_PB5 3 &pcfg_pull_none>, + <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txd1m0 */ - <3 RK_PB6 3 &pcfg_pull_none>, + <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txd2m0 */ - <3 RK_PA2 3 &pcfg_pull_none>, + <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txd3m0 */ - <3 RK_PA3 3 &pcfg_pull_none>, + <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txenm0 */ <3 RK_PB7 3 &pcfg_pull_none>; }; - gmac1m1_pins: gmac1m1-pins { + gmac1m1_miim_pins: gmac1m1-miim-pins { rockchip,pins = - /* gmac1_mclkinoutm1 */ - <4 RK_PC1 3 &pcfg_pull_none>, /* gmac1_mdcm1 */ <4 RK_PB6 3 &pcfg_pull_none>, /* gmac1_mdiom1 */ - <4 RK_PB7 3 &pcfg_pull_none>, + <4 RK_PB7 3 &pcfg_pull_none>; + }; + gmac1m1_rmii_pins: gmac1m1-rmii-pins { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none>, + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxerm1 */ + <4 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + gmac1m1_rgmii_pins: gmac1m1-rgmii-pins { + rockchip,pins = /* gmac1_rxclkm1 */ <4 RK_PA3 3 &pcfg_pull_none>, /* gmac1_rxd0m1 */ @@ -558,18 +599,16 @@ <4 RK_PA2 3 &pcfg_pull_none>, /* gmac1_rxdvcrsm1 */ <4 RK_PB1 3 &pcfg_pull_none>, - /* gmac1_rxerm1 */ - <4 RK_PB2 3 &pcfg_pull_none>, /* gmac1_txclkm1 */ - <4 RK_PA0 3 &pcfg_pull_none>, + <4 RK_PA0 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txd0m1 */ - <4 RK_PA4 3 &pcfg_pull_none>, + <4 RK_PA4 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txd1m1 */ - <4 RK_PA5 3 &pcfg_pull_none>, + <4 RK_PA5 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txd2m1 */ - <3 RK_PD6 3 &pcfg_pull_none>, + <3 RK_PD6 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txd3m1 */ - <3 RK_PD7 3 &pcfg_pull_none>, + <3 RK_PD7 3 &pcfg_pull_none_drv_level_15>, /* gmac1_txenm1 */ <4 RK_PA6 3 &pcfg_pull_none>; }; @@ -584,12 +623,12 @@ }; }; hdmitx { - hdmitxm0_pins: hdmitxm0-pins { + hdmitxm0_cec: hdmitxm0-cec { rockchip,pins = /* hdmitx_cecm0 */ <4 RK_PD1 1 &pcfg_pull_none>; }; - hdmitxm1_pins: hdmitxm1-pins { + hdmitxm1_cec: hdmitxm1-cec { rockchip,pins = /* hdmitx_cecm1 */ <0 RK_PC7 1 &pcfg_pull_none>; @@ -1475,7 +1514,7 @@ sdmmc0_clk: sdmmc0-clk { rockchip,pins = /* sdmmc0_clk */ - <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + <2 RK_PA2 1 &pcfg_pull_up_drv_level_1>; }; sdmmc0_cmd: sdmmc0-cmd { rockchip,pins = @@ -1495,23 +1534,23 @@ sdmmc1_bus4: sdmmc1-bus4 { rockchip,pins = /* sdmmc1_d0 */ - <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + <2 RK_PA3 1 &pcfg_pull_up_drv_level_5>, /* sdmmc1_d1 */ - <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + <2 RK_PA4 1 &pcfg_pull_up_drv_level_5>, /* sdmmc1_d2 */ - <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + <2 RK_PA5 1 &pcfg_pull_up_drv_level_5>, /* sdmmc1_d3 */ - <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; + <2 RK_PA6 1 &pcfg_pull_up_drv_level_5>; }; sdmmc1_clk: sdmmc1-clk { rockchip,pins = /* sdmmc1_clk */ - <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + <2 RK_PB0 1 &pcfg_pull_up_drv_level_5>; }; sdmmc1_cmd: sdmmc1-cmd { rockchip,pins = /* sdmmc1_cmd */ - <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + <2 RK_PA7 1 &pcfg_pull_up_drv_level_5>; }; sdmmc1_det: sdmmc1-det { rockchip,pins = @@ -1526,23 +1565,23 @@ sdmmc2m0_bus4: sdmmc2m0-bus4 { rockchip,pins = /* sdmmc2_d0m0 */ - <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, + <3 RK_PC6 3 &pcfg_pull_up_drv_level_5>, /* sdmmc2_d1m0 */ - <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, + <3 RK_PC7 3 &pcfg_pull_up_drv_level_5>, /* sdmmc2_d2m0 */ - <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, + <3 RK_PD0 3 &pcfg_pull_up_drv_level_5>, /* sdmmc2_d3m0 */ - <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; + <3 RK_PD1 3 &pcfg_pull_up_drv_level_5>; }; sdmmc2m0_clk: sdmmc2m0-clk { rockchip,pins = /* sdmmc2_clkm0 */ - <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; + <3 RK_PD3 3 &pcfg_pull_up_drv_level_5>; }; sdmmc2m0_cmd: sdmmc2m0-cmd { rockchip,pins = /* sdmmc2_cmdm0 */ - <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; + <3 RK_PD2 3 &pcfg_pull_up_drv_level_5>; }; sdmmc2detm0: sdmmc2detm0 { rockchip,pins = @@ -1555,23 +1594,23 @@ sdmmc2m1_bus4: sdmmc2m1-bus4 { rockchip,pins = /* sdmmc2_d0m1 */ - <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + <3 RK_PA1 5 &pcfg_pull_up_drv_level_5>, /* sdmmc2_d1m1 */ - <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + <3 RK_PA2 5 &pcfg_pull_up_drv_level_5>, /* sdmmc2_d2m1 */ - <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, + <3 RK_PA3 5 &pcfg_pull_up_drv_level_5>, /* sdmmc2_d3m1 */ - <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; + <3 RK_PA4 5 &pcfg_pull_up_drv_level_5>; }; sdmmc2m1_clk: sdmmc2m1-clk { rockchip,pins = /* sdmmc2_clkm1 */ - <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; + <3 RK_PA6 5 &pcfg_pull_up_drv_level_5>; }; sdmmc2m1_cmd: sdmmc2m1-cmd { rockchip,pins = /* sdmmc2_cmdm1 */ - <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; + <3 RK_PA5 5 &pcfg_pull_up_drv_level_5>; }; sdmmc2detm1: sdmmc2detm1 { rockchip,pins = @@ -1620,6 +1659,18 @@ rockchip,pins = <0 RK_PB6 2 &pcfg_pull_none>; }; + spi0clkm0_hs: spi0clkm0-hs { + rockchip,pins = + <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>; + }; + spi0misom0_hs: spi0misom0-hs { + rockchip,pins = + <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>; + }; + spi0mosim0_hs: spi0mosim0-hs { + rockchip,pins = + <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; + }; spi0clkm1: spi0clkm1 { rockchip,pins = <2 RK_PD3 3 &pcfg_pull_none>; @@ -1636,6 +1687,18 @@ rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; }; + spi0clkm1_hs: spi0clkm1-hs { + rockchip,pins = + <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>; + }; + spi0misom1_hs: spi0misom1-hs { + rockchip,pins = + <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>; + }; + spi0mosim1_hs: spi0mosim1-hs { + rockchip,pins = + <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; + }; }; spi1 { spi1clkm0: spi1clkm0 { @@ -1658,6 +1721,18 @@ rockchip,pins = <2 RK_PB7 4 &pcfg_pull_none>; }; + spi1clkm0_hs: spi1clkm0-hs { + rockchip,pins = + <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>; + }; + spi1misom0_hs: spi1misom0-hs { + rockchip,pins = + <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>; + }; + spi1mosim0_hs: spi1mosim0-hs { + rockchip,pins = + <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; + }; spi1clkm1: spi1clkm1 { rockchip,pins = <3 RK_PC3 3 &pcfg_pull_none>; @@ -1674,6 +1749,18 @@ rockchip,pins = <3 RK_PC1 3 &pcfg_pull_none>; }; + spi1clkm1_hs: spi1clkm1-hs { + rockchip,pins = + <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>; + }; + spi1misom1_hs: spi1misom1-hs { + rockchip,pins = + <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>; + }; + spi1mosim1_hs: spi1mosim1-hs { + rockchip,pins = + <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; + }; }; spi2 { spi2clkm0: spi2clkm0 { @@ -1696,6 +1783,18 @@ rockchip,pins = <2 RK_PC3 4 &pcfg_pull_none>; }; + spi2clkm0_hs: spi2clkm0-hs { + rockchip,pins = + <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>; + }; + spi2misom0_hs: spi2misom0-hs { + rockchip,pins = + <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>; + }; + spi2mosim0_hs: spi2mosim0-hs { + rockchip,pins = + <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; + }; spi2clkm1: spi2clkm1 { rockchip,pins = <3 RK_PA0 3 &pcfg_pull_none>; @@ -1716,6 +1815,18 @@ rockchip,pins = <2 RK_PD6 3 &pcfg_pull_none>; }; + spi2clkm1_hs: spi2clkm1-hs { + rockchip,pins = + <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>; + }; + spi2misom1_hs: spi2misom1-hs { + rockchip,pins = + <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>; + }; + spi2mosim1_hs: spi2mosim1-hs { + rockchip,pins = + <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; + }; }; spi3 { spi3clkm0: spi3clkm0 { @@ -1738,6 +1849,18 @@ rockchip,pins = <4 RK_PB2 4 &pcfg_pull_none>; }; + spi3clkm0_hs: spi3clkm0-hs { + rockchip,pins = + <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>; + }; + spi3misom0_hs: spi3misom0-hs { + rockchip,pins = + <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>; + }; + spi3mosim0_hs: spi3mosim0-hs { + rockchip,pins = + <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; + }; spi3clkm1: spi3clkm1 { rockchip,pins = <4 RK_PC2 2 &pcfg_pull_none>; @@ -1758,8 +1881,23 @@ rockchip,pins = <4 RK_PC3 2 &pcfg_pull_none>; }; + spi3clkm1_hs: spi3clkm1-hs { + rockchip,pins = + <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>; + }; + spi3misom1_hs: spi3misom1-hs { + rockchip,pins = + <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>; + }; + spi3mosim1_hs: spi3mosim1-hs { + rockchip,pins = + <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; + }; }; tsadc { + tsadc_gpio: tsadc-gpio { + rockchip,pins = <0 RK_PA1 0 &pcfg_pull_none>; + }; tsadcm0_pins: tsadcm0-pins { rockchip,pins = /* tsadc_shutm0 */ diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi index a462fdf9b1..3b4a7b62e5 100644 --- a/arch/arm/dts/rk3568.dtsi +++ b/arch/arm/dts/rk3568.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include / { @@ -17,12 +19,23 @@ #size-cells = <2>; aliases { + dsi0 = &dsi0; + dsi1 = &dsi1; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + lvds0 = &lvds0; + lvds1 = &lvds1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -48,13 +61,17 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; -#if 0 + cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@200 { @@ -62,6 +79,8 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x200>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@300 { @@ -69,11 +88,43 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x300>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1000000 1000000 1250000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000 1000000 1250000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000 1000000 1250000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1000000 1000000 1250000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000 1000000 1250000>; + clock-latency-ns = <40000>; }; -#endif }; -#if 0 arm-pmu { compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; interrupts = , @@ -82,13 +133,49 @@ ; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; -#endif + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <5>; + rockchip,resetgroup-count = <5>; + status = "disabled"; + }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + trips { + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -97,6 +184,20 @@ ; }; + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + #clock-cells = <0>; + }; + + gmac1_clkini: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + xin24m: xin24m { compatible = "fixed-clock"; #clock-cells = <0>; @@ -104,6 +205,51 @@ clock-output-names = "xin24m"; }; + sata0: sata@fc000000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc000000 0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, + <&cru CLK_SATA0_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy0_us PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + sata1: sata@fc400000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, + <&cru CLK_SATA1_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy1_usq PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + sata2: sata@fc800000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc800000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, + <&cru CLK_SATA2_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy2_psq PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + usbdrd30: usbdrd { compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, @@ -183,6 +329,7 @@ compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0xfd440000 0x0 0x20000>; + status = "disabled"; }; }; @@ -190,10 +337,11 @@ compatible = "generic-ehci"; reg = <0x0 0xfd800000 0x0 0x40000>; interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>; - clock-names = "usbhost", "arbiter"; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; phys = <&u2phy1_otg>; - phy-names = "usb"; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -201,10 +349,11 @@ compatible = "generic-ohci"; reg = <0x0 0xfd840000 0x0 0x40000>; interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>; - clock-names = "usbhost", "arbiter"; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; phys = <&u2phy1_otg>; - phy-names = "usb"; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -212,10 +361,11 @@ compatible = "generic-ehci"; reg = <0x0 0xfd880000 0x0 0x40000>; interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>; - clock-names = "usbhost", "arbiter"; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; phys = <&u2phy1_host>; - phy-names = "usb"; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -223,21 +373,36 @@ compatible = "generic-ohci"; reg = <0x0 0xfd8c0000 0x0 0x40000>; interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>; - clock-names = "usbhost", "arbiter"; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; phys = <&u2phy1_host>; - phy-names = "usb"; + phy-names = "usb2-phy"; status = "disabled"; }; pmugrf: syscon@fdc20000 { - compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfdc20000 0x0 0x10000>; pmu_io_domains: io-domains { compatible = "rockchip,rk3568-pmu-io-voltage-domain"; status = "disabled"; }; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + mode-panic = ; + mode-watchdog = ; + }; }; pipegrf: syscon@fdc50000 { @@ -253,6 +418,87 @@ compatible = "rockchip,rk3568-io-voltage-domain"; status = "disabled"; }; + + lvds0: lvds0 { + compatible = "rockchip,rk3568-lvds"; + phys = <&video_phy0>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds0_in_vp1: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp1_out_lvds0>; + }; + + lvds0_in_vp2: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp2_out_lvds0>; + }; + }; + }; + }; + + lvds1: lvds1 { + compatible = "rockchip,rk3568-lvds"; + phys = <&video_phy1>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds1_in_vp1: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp1_out_lvds1>; + }; + + lvds1_in_vp2: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp2_out_lvds1>; + }; + }; + }; + }; + + rgb: rgb { + compatible = "rockchip,rk3568-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vp2: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp2_out_rgb>; + }; + }; + + }; + }; + }; pipe_phy_grf0: syscon@fdc70000 { @@ -280,6 +526,22 @@ reg = <0x0 0xfdca8000 0x0 0x8000>; }; + edp_phy: edp-phy@fdcb0000 { + compatible = "rockchip,rk3568-edp-phy"; + reg = <0x0 0xfdcb0000 0x0 0x8000>; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>; + clock-names = "refclk", "pclk"; + resets = <&cru SRST_P_EDPPHY_GRF>; + reset-names = "apb"; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie30_phy_grf: syscon@fdcb8000 { + compatible = "rockchip,pcie30-phy-grf", "syscon"; + reg = <0x0 0xfdcb8000 0x0 0x10000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -302,15 +564,17 @@ <&cru ACLK_BUS>, <&cru PCLK_BUS>, <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, <&cru HCLK_TOP>, <&cru PCLK_TOP>, - <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>; + <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, + <&cru PLL_NPLL>; assigned-clock-rates = - <32768>, <100000000>, + <32768>, <200000000>, <100000000>, <1000000000>, <1188000000>, <600000000>, <150000000>, <100000000>, <300000000>, <200000000>, <150000000>, <100000000>, - <300000000>, <150000000>; + <300000000>, <150000000>, + <1200000000>; assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; }; @@ -400,28 +664,40 @@ /* These power domains are grouped by VD_NPU */ pd_npu@RK3568_PD_NPU { reg = ; + clocks = <&cru ACLK_NPU_PRE>, + <&cru HCLK_NPU_PRE>, + <&cru PCLK_NPU_PRE>; pm_qos = <&qos_npu>; }; /* These power domains are grouped by VD_GPU */ pd_gpu@RK3568_PD_GPU { reg = ; + clocks = <&cru ACLK_GPU_PRE>, + <&cru PCLK_GPU_PRE>; pm_qos = <&qos_gpu>; }; /* These power domains are grouped by VD_LOGIC */ pd_vi@RK3568_PD_VI { reg = ; + clocks = <&cru HCLK_VI>, + <&cru PCLK_VI>; pm_qos = <&qos_isp>, <&qos_vicap0>, <&qos_vicap1>; }; pd_vo@RK3568_PD_VO { reg = ; + clocks = <&cru HCLK_VO>, + <&cru PCLK_VO>, + <&cru ACLK_VOP_PRE>; pm_qos = <&qos_hdcp>, <&qos_vop_m0>, <&qos_vop_m1>; }; pd_rga@RK3568_PD_RGA { reg = ; + clocks = <&cru HCLK_RGA_PRE>, + <&cru PCLK_RGA_PRE>; pm_qos = <&qos_ebc>, <&qos_iep>, <&qos_jpeg_dec>, @@ -431,20 +707,24 @@ }; pd_vpu@RK3568_PD_VPU { reg = ; + clocks = <&cru HCLK_VPU_PRE>; pm_qos = <&qos_vpu>; }; pd_rkvdec@RK3568_PD_RKVDEC { + clocks = <&cru HCLK_RKVDEC_PRE>; reg = ; pm_qos = <&qos_rkvdec>; }; pd_rkvenc@RK3568_PD_RKVENC { reg = ; + clocks = <&cru HCLK_RKVENC_PRE>; pm_qos = <&qos_rkvenc_rd_m0>, <&qos_rkvenc_rd_m1>, <&qos_rkvenc_wr_m0>; }; pd_pipe@RK3568_PD_PIPE { reg = ; + clocks = <&cru PCLK_PIPE>; pm_qos = <&qos_pcie2x1>, <&qos_pcie3x1>, <&qos_pcie3x2>, @@ -457,6 +737,21 @@ }; }; + pvtm@fde00000 { + compatible = "rockchip,rk3568-core-pvtm"; + reg = <0x0 0xfde00000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@0 { + reg = <0>; + clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>; + reset-names = "rts", "rst-p"; + thermal-zone = "soc-thermal"; + }; + }; + gpu: gpu@fde60000 { compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; reg = <0x0 0xfde60000 0x0 0x4000>; @@ -506,6 +801,702 @@ }; }; + pvtm@fde80000 { + compatible = "rockchip,rk3568-gpu-pvtm"; + reg = <0x0 0xfde80000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@1 { + reg = <1>; + clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; + reset-names = "rts", "rst-p"; + thermal-zone = "gpu-thermal"; + }; + }; + + pvtm@fde90000 { + compatible = "rockchip,rk3568-npu-pvtm"; + reg = <0x0 0xfde90000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@2 { + reg = <2>; + clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>, + <&cru HCLK_NPU_PRE>; + clock-names = "clk", "pclk", "hclk"; + resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; + reset-names = "rts", "rst-p"; + thermal-zone = "soc-thermal"; + }; + }; + + vdpu: vdpu@fdea0400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xfdea0400 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; + reset-names = "video_a", "video_h"; + iommus = <&vdpu_mmu>; + power-domains = <&power RK3568_PD_VPU>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + status = "disabled"; + }; + + vdpu_mmu: iommu@fdea0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdea0800 0x0 0x40>; + interrupts = ; + interrupt-names = "vdpu_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + power-domains = <&power RK3568_PD_VPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rk_rga: rk_rga@fdeb0000 { + compatible = "rockchip,rga2"; + reg = <0x0 0xfdeb0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power RK3568_PD_RGA>; + status = "disabled"; + }; + + ebc: ebc@fdec0000 { + compatible = "rockchip,rk3568-ebc-tcon"; + reg = <0x0 0xfdec0000 0x0 0x5000>; + interrupts = ; + clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>; + clock-names = "hclk", "dclk"; + power-domains = <&power RK3568_PD_RGA>; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&ebc_pins>; + status = "disabled"; + }; + + jpegd: jpegd@fded0000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x0 0xfded0000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <297000000>, <0>; + resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; + reset-names = "video_a", "video_h"; + iommus = <&jpegd_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <1>; + rockchip,resetgroup-node = <1>; + power-domains = <&power RK3568_PD_RGA>; + status = "disabled"; + }; + + jpegd_mmu: iommu@fded0480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfded0480 0x0 0x40>; + interrupts = ; + interrupt-names = "jpegd_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; + power-domains = <&power RK3568_PD_RGA>; + #iommu-cells = <0>; + status = "disabled"; + }; + + vepu: vepu@fdee0000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x0 0xfdee0000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <297000000>, <0>; + resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>; + reset-names = "video_a", "video_h"; + iommus = <&vepu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,resetgroup-node = <2>; + power-domains = <&power RK3568_PD_RGA>; + status = "disabled"; + }; + + vepu_mmu: iommu@fdee0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdee0800 0x0 0x40>; + interrupts = ; + interrupt-names = "vepu_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; + power-domains = <&power RK3568_PD_RGA>; + #iommu-cells = <0>; + status = "disabled"; + }; + + iep: iep@fdef0000 { + compatible = "rockchip,iep-v2"; + reg = <0x0 0xfdef0000 0x0 0x500>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>, + <&cru SRST_IEP_CORE>; + reset-names = "rst_a", "rst_h", "rst_s"; + power-domains = <&power RK3568_PD_RGA>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <5>; + rockchip,resetgroup-node = <5>; + iommus = <&iep_mmu>; + status = "disabled"; + }; + + iep_mmu: iommu@fdef0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdef0800 0x0 0x100>; + interrupts = ; + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3568_PD_RGA>; + //rockchip,disable-device-link-resume; + status = "disabled"; + }; + + eink: eink@fdf00000 { + compatible = "rockchip,rk3568-eink-tcon"; + reg = <0x0 0xfdf00000 0x0 0x74>; + interrupts = ; + clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + rkvenc: rkvenc@fdf40000 { + compatible = "rockchip,rkv-encoder-v1"; + reg = <0x0 0xfdf40000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_enc"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, + <&cru CLK_RKVENC_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <297000000>, <0>, <400000000>; + rockchip,advanced-rates = <297000000>, <0>, <500000000>; + rockchip,default-max-load = <2088960>; + resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, + <&cru SRST_RKVENC_CORE>; + reset-names = "video_a", "video_h", "video_core"; + assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; + assigned-clock-rates = <297000000>, <297000000>; + iommus = <&rkvenc_mmu>; + node-name = "rkvenc"; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <3>; + rockchip,resetgroup-node = <3>; + power-domains = <&power RK3568_PD_RKVENC>; + status = "disabled"; + }; + + rkvenc_mmu: iommu@fdf40f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>; + interrupts = , + ; + interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + #iommu-cells = <0>; + power-domains = <&power RK3568_PD_RKVENC>; + status = "disabled"; + }; + + rkvdec: rkvdec@fdf80200 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdf80200 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac", + "clk_core", "clk_hevc_cabac"; + rockchip,normal-rates = <297000000>, <0>, <297000000>, + <297000000>, <400000000>; + rockchip,advanced-rates = <400000000>, <0>, <400000000>, + <400000000>, <500000000>; + rockchip,default-max-load = <2088960>; + resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, + <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>, + <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>; + reset-names = "video_a", "video_h", "video_cabac", + "video_core", "video_hevc_cabac"; + power-domains = <&power RK3568_PD_RKVDEC>; + iommus = <&rkvdec_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <4>; + rockchip,resetgroup-node = <4>; + status = "disabled"; + }; + + rkvdec_mmu: iommu@fdf80800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3568_PD_RKVDEC>; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi_csi2: mipi-csi2@fdfb0000 { + compatible = "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdfb0000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI2HOST1>, <&cru SRST_P_CSI2HOST1>; + clock-names = "pclk_csi2host", "srst_csihost_p"; + power-domains = <&power RK3568_PD_VI>; + status = "disabled"; + }; + + rkcif: rkcif@fdfe0000 { + compatible = "rockchip,rk3568-cif"; + reg = <0x0 0xfdfe0000 0x0 0x8000>; + reg-names = "cif_regs"; + interrupts = ; + interrupt-names = "cif-intr"; + + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; + clock-names = "aclk_cif", "hclk_cif", + "dclk_cif", "iclk_cif_g"; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, + <&cru SRST_I_VICAP>; + reset-names = "rst_cif_a", "rst_cif_h", + "rst_cif_d", "rst_cif_p", + "rst_cif_i"; + assigned-clocks = <&cru DCLK_VICAP>; + assigned-clock-rates = <300000000>; + power-domains = <&power RK3568_PD_VI>; + rockchip,grf = <&grf>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mmu: iommu@fdfe0800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xfdfe0800 0x0 0x100>; + interrupts = ; + interrupt-names = "cif_mmu"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3568_PD_VI>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkcif_dvp: rkcif_dvp { + compatible = "rockchip,rkcif-dvp"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_dvp_sditf: rkcif_dvp_sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_dvp>; + status = "disabled"; + }; + + rkcif_mipi_lvds: rkcif_mipi_lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkisp: rkisp@fdff0000 { + compatible = "rockchip,rk3568-rkisp"; + reg = <0x0 0xfdff0000 0x0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp"; + resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>; + reset-names = "isp", "isp-h"; + rockchip,grf = <&grf>; + power-domains = <&power RK3568_PD_VI>; + iommus = <&rkisp_mmu>; + status = "disabled"; + }; + + rkisp_mmu: iommu@fdff1a00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xfdff1a00 0x0 0x100>; + interrupts = ; + interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3568_PD_VI>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkisp_vir0: rkisp-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rkisp_vir1: rkisp-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + gmac1: ethernet@fe010000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe010000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, + <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + vop: vop@fe040000 { + compatible = "rockchip,rk3568-vop"; + reg = <0x0 0xfe040000 0x0 0x3000>; + reg-names = "regs"; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3568_PD_VO>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vp0_out_dsi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_in_vp0>; + }; + + vp0_out_dsi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi1_in_vp0>; + }; + + vp0_out_edp: endpoint@2 { + reg = <2>; + remote-endpoint = <&edp_in_vp0>; + }; + + vp0_out_hdmi: endpoint@3 { + reg = <3>; + remote-endpoint = <&hdmi_in_vp0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vp1_out_dsi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_in_vp1>; + }; + + vp1_out_dsi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi1_in_vp1>; + }; + + vp1_out_edp: endpoint@2 { + reg = <2>; + remote-endpoint = <&edp_in_vp1>; + }; + + vp1_out_hdmi: endpoint@3 { + reg = <3>; + remote-endpoint = <&hdmi_in_vp1>; + }; + + vp1_out_lvds0: endpoint@4 { + reg = <4>; + remote-endpoint = <&lvds0_in_vp1>; + }; + + vp1_out_lvds1: endpoint@5 { + reg = <5>; + remote-endpoint = <&lvds1_in_vp1>; + }; + + }; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vp2_out_lvds0: endpoint@0 { + reg = <0>; + remote-endpoint = <&lvds0_in_vp2>; + }; + + vp2_out_lvds1: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds1_in_vp2>; + }; + + vp2_out_rgb: endpoint@2 { + reg = <2>; + remote-endpoint = <&rgb_in_vp2>; + }; + }; + }; + }; + + vop_mmu: iommu@fe043e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + dsi0: dsi@fe060000 { + compatible = "rockchip,rk3568-mipi-dsi"; + reg = <0x0 0xfe060000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&mipi_dphy0>; + clock-names = "pclk", "hclk", "hs_clk"; + resets = <&cru SRST_P_DSITX_0>; + reset-names = "apb"; + phys = <&mipi_dphy0>; + phy-names = "mipi_dphy"; + power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dsi0>; + }; + + dsi0_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dsi0>; + }; + }; + }; + }; + + dsi1: dsi@fe070000 { + compatible = "rockchip,rk3568-mipi-dsi"; + reg = <0x0 0xfe070000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&mipi_dphy1>; + clock-names = "pclk", "hclk", "hs_clk"; + resets = <&cru SRST_P_DSITX_1>; + reset-names = "apb"; + phys = <&mipi_dphy1>; + phy-names = "mipi_dphy"; + power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dsi1>; + }; + + dsi1_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dsi1>; + }; + }; + }; + }; + + hdmi: hdmi@fe0a0000 { + compatible = "rockchip,rk3568-dw-hdmi"; + reg = <0x0 0xfe0a0000 0x0 0x20000>; + interrupts = ; + clocks = <&cru PCLK_HDMI_HOST>, + <&cru CLK_HDMI_SFR>, + <&cru CLK_HDMI_CEC>, + <&pmucru PLL_HPLL>, + <&cru HCLK_VOP>; + clock-names = "iahb", "isfr", "cec", "ref", "hclk"; + power-domains = <&power RK3568_PD_VO>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_hdmi>; + }; + hdmi_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_hdmi>; + }; + }; + }; + }; + + edp: edp@fe0c0000 { + compatible = "rockchip,rk3568-edp"; + reg = <0x0 0xfe0c0000 0x0 0x10000>; + interrupts = ; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>, + <&cru CLK_EDP_200M>, <&cru HCLK_VO>; + clock-names = "dp", "pclk", "spdif", "hclk"; + resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>; + reset-names = "dp", "apb"; + phys = <&edp_phy>; + phy-names = "dp"; + power-domains = <&power RK3568_PD_VO>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_edp>; + }; + + edp_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_edp>; + }; + }; + }; + }; + qos_gpu: qos@fe128000 { compatible = "syscon"; reg = <0x0 0xfe128000 0x0 0x20>; @@ -656,6 +1647,165 @@ status = "disabled"; }; + pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x1f>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + linux,pci-domain = <0>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <2>; + msi-map = <0x0 &its 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psq PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + ranges = <0x00000800 0x0 0x00000000 0x3 0x00000000 0x0 0x800000 + 0x81000000 0x0 0x00800000 0x3 0x00800000 0x0 0x100000 + 0x83000000 0x0 0x00900000 0x3 0x00900000 0x0 0x3f700000>; + reg = <0x3 0xc0000000 0x0 0x400000>, + <0x0 0xfe260000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + status = "disabled"; + }; + + pcie3x1: pcie@fe270000 { + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x1f>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + linux,pci-domain = <1>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &its 0x3000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + ranges = <0x00000800 0x0 0x40000000 0x3 0x40000000 0x0 0x800000 + 0x81000000 0x0 0x40800000 0x3 0x40800000 0x0 0x100000 + 0x83000000 0x0 0x40900000 0x3 0x40900000 0x0 0x3f700000>; + reg = <0x3 0xc0400000 0x0 0x400000>, + <0x0 0xfe270000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE30X1_POWERUP>; + reset-names = "pipe"; + /* rockchip,bifurcation; lane1 when using 1+1 */ + status = "disabled"; + }; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x1f>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + linux,pci-domain = <2>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &its 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000 + 0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000 + 0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; + reg = <0x3 0xc0800000 0x0 0x400000>, + <0x0 0xfe280000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE30X2_POWERUP>; + reset-names = "pipe"; + /* rockchip,bifurcation; lane0 when using 1+1 */ + status = "disabled"; + }; + + gmac0: ethernet@fe2a0000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe2a0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, + <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + sdmmc0: dwmmc@fe2b0000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; @@ -701,8 +1851,8 @@ compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci"; reg = <0x0 0xfe310000 0x0 0x10000>; interrupts = ; - assigned-clocks = <&cru CCLK_EMMC>, <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; - assigned-clock-rates = <200000000>, <200000000>, <24000000>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>; clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; @@ -733,6 +1883,7 @@ rockchip,cru = <&cru>; rockchip,grf = <&grf>; rockchip,playback-only; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -748,6 +1899,7 @@ reset-names = "tx-m", "rx-m"; rockchip,cru = <&cru>; rockchip,grf = <&grf>; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s1sclktxm0 &i2s1sclkrxm0 @@ -775,6 +1927,7 @@ rockchip,cru = <&cru>; rockchip,grf = <&grf>; rockchip,clk-trcm = <1>; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s2sclktxm0 &i2s2lrcktxm0 @@ -795,6 +1948,7 @@ reset-names = "tx-m", "rx-m"; rockchip,cru = <&cru>; rockchip,grf = <&grf>; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s3sclkm0 &i2s3lrckm0 @@ -810,17 +1964,33 @@ clock-names = "pdm_clk", "pdm_hclk"; dmas = <&dmac1 9>; dma-names = "rx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + vad: vad@fe450000 { + compatible = "rockchip,rk3568-vad"; + reg = <0x0 0xfe450000 0x0 0x10000>; + reg-names = "vad"; + clocks = <&cru HCLK_VAD>; + clock-names = "hclk"; + interrupts = ; + rockchip,audio-src = <0>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; + #sound-dai-cells = <0>; status = "disabled"; }; spdif_8ch: spdif@fe460000 { - compatible = "rockchip,rk3588-spdif"; + compatible = "rockchip,rk3568-spdif"; reg = <0x0 0xfe460000 0x0 0x1000>; interrupts = ; dmas = <&dmac1 1>; dma-names = "tx"; clock-names = "mclk", "hclk"; clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spdifm0_pins>; status = "disabled"; @@ -833,6 +2003,7 @@ clock-names = "clk", "hclk"; dmas = <&dmac1 8>; dma-names = "tx"; + #sound-dai-cells = <0>; rockchip,sample-width-bits = <11>; rockchip,interpolat-points = <1>; status = "disabled"; @@ -841,13 +2012,15 @@ dig_acodec: codec-digital@fe478000 { compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1"; reg = <0x0 0xfe478000 0x0 0x1000>; - clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, <&cru HCLK_ACDCDIG>; - clock-names = "adc", "dac", "pclk"; + clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, + <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>; + clock-names = "adc", "dac", "i2c", "pclk"; pinctrl-names = "default"; pinctrl-0 = <&acodec_pins>; resets = <&cru SRST_ACDCDIG>; reset-names = "reset" ; rockchip,grf = <&grf>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -856,7 +2029,7 @@ reg = <0x0 0xfe530000 0x0 0x4000>; interrupts = , ; - clocks = <&cru ACLK_DMAC0>; + clocks = <&cru ACLK_BUS>; clock-names = "apb_pclk"; #dma-cells = <1>; arm,pl330-periph-burst; @@ -867,7 +2040,7 @@ reg = <0x0 0xfe550000 0x0 0x4000>; interrupts = , ; - clocks = <&cru ACLK_DMAC1>; + clocks = <&cru ACLK_BUS>; clock-names = "apb_pclk"; #dma-cells = <1>; arm,pl330-periph-burst; @@ -980,7 +2153,8 @@ wdt: watchdog@fe600000 { compatible = "snps,dw-wdt"; reg = <0x0 0xfe600000 0x0 0x100>; - clocks = <&cru PCLK_WDT_NS>; + clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; + clock-names = "tclk", "pclk"; interrupts = ; status = "okay"; }; @@ -994,8 +2168,10 @@ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; dmas = <&dmac0 20>, <&dmac0 21>; - pinctrl-names = "default"; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>; + pinctrl-1 = <&spi0clkm0_hs &spi0cs0m0 &spi0cs1m0 &spi0misom0_hs &spi0mosim0_hs>; status = "disabled"; }; @@ -1008,8 +2184,10 @@ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; dmas = <&dmac0 22>, <&dmac0 23>; - pinctrl-names = "default"; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>; + pinctrl-1 = <&spi1clkm0_hs &spi1cs0m0 &spi1cs1m0 &spi1misom0_hs &spi1mosim0_hs>; status = "disabled"; }; @@ -1022,8 +2200,10 @@ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; dmas = <&dmac0 24>, <&dmac0 25>; - pinctrl-names = "default"; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>; + pinctrl-1 = <&spi2clkm0_hs &spi2cs0m0 &spi2cs1m0 &spi2misom0_hs &spi2mosim0_hs>; status = "disabled"; }; @@ -1036,8 +2216,10 @@ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; clock-names = "spiclk", "apb_pclk"; dmas = <&dmac0 26>, <&dmac0 27>; - pinctrl-names = "default"; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>; + pinctrl-1 = <&spi3clkm0_hs &spi3cs0m0 &spi3cs1m0 &spi3misom0_hs &spi3mosim0_hs>; status = "disabled"; }; @@ -1299,6 +2481,28 @@ status = "disabled"; }; + tsadc: tsadc@fe710000 { + compatible = "rockchip,rk3568-tsadc"; + reg = <0x0 0xfe710000 0x0 0x100>; + interrupts = ; + rockchip,grf = <&grf>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; + assigned-clock-rates = <17000000>, <700000>; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, + <&cru SRST_TSADCPHY>; + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_gpio>; + pinctrl-1 = <&tsadc_shutorg>; + status = "disabled"; + }; + saradc: saradc@fe720000 { compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xfe720000 0x0 0x100>; @@ -1311,12 +2515,28 @@ status = "disabled"; }; + mailbox: mailbox@fe780000 { + compatible = "rockchip,rk3568-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfe780000 0x0 0x1000>; + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + combphy0_us: phy@fe820000 { compatible = "rockchip,rk3568-naneng-combphy"; reg = <0x0 0xfe820000 0x0 0x100>; #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>; clock-names = "refclk", "apbclk"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <24000000>; resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&pipegrf>; @@ -1330,7 +2550,9 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>; clock-names = "refclk", "apbclk"; - resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <24000000>; + resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; @@ -1343,6 +2565,8 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>; clock-names = "refclk", "apbclk"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <24000000>; resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&pipegrf>; @@ -1350,6 +2574,75 @@ status = "disabled"; }; + mipi_dphy0: mipi-dphy@fe850000 { + compatible = "rockchip,rk3568-mipi-dphy"; + reg = <0x0 0xfe850000 0x0 0x10000>; + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; + clock-names = "ref", "pclk"; + clock-output-names = "mipi_dphy_pll"; + #clock-cells = <0>; + resets = <&cru SRST_P_MIPIDSIPHY0>; + reset-names = "apb"; + power-domains = <&power RK3568_PD_VO>; + #phy-cells = <0>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + video_phy0: video-phy@fe850000 { + compatible = "rockchip,rk3568-video-phy"; + reg = <0x0 0xfe850000 0x0 0x10000>, + <0x0 0xfe060000 0x0 0x10000>; + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, + <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>; + clock-names = "ref", "pclk_phy", "pclk_host"; + #clock-cells = <0>; + resets = <&cru SRST_P_MIPIDSIPHY0>; + reset-names = "rst"; + power-domains = <&power RK3568_PD_VO>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dphy1: mipi-dphy@fe860000 { + compatible = "rockchip,rk3568-mipi-dphy"; + reg = <0x0 0xfe860000 0x0 0x10000>; + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; + clock-names = "ref", "pclk"; + clock-output-names = "mipi_dphy1_pll"; + #clock-cells = <0>; + resets = <&cru SRST_P_MIPIDSIPHY1>; + reset-names = "apb"; + power-domains = <&power RK3568_PD_VO>; + #phy-cells = <0>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + video_phy1: video-phy@fe860000 { + compatible = "rockchip,rk3568-video-phy"; + reg = <0x0 0xfe860000 0x0 0x10000>, + <0x0 0xfe070000 0x0 0x10000>; + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, + <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>; + clock-names = "ref", "pclk_phy", "pclk_host"; + #clock-cells = <0>; + resets = <&cru SRST_P_MIPIDSIPHY1>; + reset-names = "rst"; + power-domains = <&power RK3568_PD_VO>; + #phy-cells = <0>; + status = "disabled"; + }; + + csi_dphy: csi-dphy@fe870000 { + compatible = "rockchip,rk3568-csi-dphy"; + reg = <0x0 0xfe870000 0x0 0x1000>; + clocks = <&cru PCLK_MIPICSIPHY>; + clock-names = "pclk"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + usb2phy0: usb2-phy@fe8a0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x0 0xfe8a0000 0x0 0x10000>; @@ -1357,18 +2650,20 @@ clocks = <&pmucru CLK_USBPHY0_REF>; clock-names = "phyclk"; #clock-cells = <0>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&usb2phy0>; clock-output-names = "usb480m_phy"; rockchip,usbgrf = <&usb2phy0_grf>; status = "disabled"; u2phy0_host: host-port { - #phy-cells = <0>; - status = "disabled"; + #phy-cells = <0>; + status = "disabled"; }; u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; + #phy-cells = <0>; + status = "disabled"; }; }; @@ -1378,6 +2673,7 @@ interrupts = ; clocks = <&pmucru CLK_USBPHY1_REF>; clock-names = "phyclk"; + #clock-cells = <0>; rockchip,usbgrf = <&usb2phy1_grf>; status = "disabled"; @@ -1392,6 +2688,19 @@ }; }; + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>; @@ -1441,7 +2750,7 @@ gpio3: gpio@fe760000 { compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe750000 0x0 0x100>; + reg = <0x0 0xfe760000 0x0 0x100>; interrupts = ; clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h index 26ec41bbbb..236c792566 100644 --- a/include/dt-bindings/clock/rk3568-cru.h +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -59,8 +59,10 @@ #define PCLK_GPIO0 46 #define PCLK_PMUPVTM 47 #define PCLK_PWM0 48 +#define CLK_PDPMU 49 +#define SCLK_32K_IOE 50 -#define CLKPMU_NR_CLKS (PCLK_PWM0 + 1) +#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) /* cru-clocks indices */ @@ -290,7 +292,6 @@ #define PCLK_HDCP 229 #define PCLK_HDMI_HOST 230 #define CLK_HDMI_SFR 231 -#define CLK_HDMI_CEC 231 #define PCLK_DSITX_0 232 #define PCLK_DSITX_1 233 #define PCLK_EDP_CTRL 234 @@ -462,7 +463,15 @@ #define SCLK_EMMC_DRV 400 #define SCLK_EMMC_SAMPLE 401 #define PCLK_EDPPHY_GRF 402 -#define PCLK_CORE_PVTM 403 +#define CLK_HDMI_CEC 403 +#define CLK_I2S0_8CH_TX 404 +#define CLK_I2S0_8CH_RX 405 +#define CLK_I2S1_8CH_TX 406 +#define CLK_I2S1_8CH_RX 407 +#define CLK_I2S2_2CH 408 +#define CLK_I2S3_2CH_TX 409 +#define CLK_I2S3_2CH_RX 410 +#define PCLK_CORE_PVTM 450 #define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) @@ -623,12 +632,42 @@ /* cru_softrst_con10 */ #define SRST_P_PCIE20 160 +#define SRST_PCIE20_POWERUP 161 +#define SRST_MSTR_ARESET_PCIE20 162 +#define SRST_SLV_ARESET_PCIE20 163 +#define SRST_DBI_ARESET_PCIE20 164 +#define SRST_BRESET_PCIE20 165 +#define SRST_PERST_PCIE20 166 +#define SRST_CORE_RST_PCIE20 167 +#define SRST_NSTICKY_RST_PCIE20 168 +#define SRST_STICKY_RST_PCIE20 169 +#define SRST_PWR_RST_PCIE20 170 /* cru_softrst_con11 */ #define SRST_P_PCIE30X1 176 +#define SRST_PCIE30X1_POWERUP 177 +#define SRST_M_ARESET_PCIE30X1 178 +#define SRST_S_ARESET_PCIE30X1 179 +#define SRST_D_ARESET_PCIE30X1 180 +#define SRST_BRESET_PCIE30X1 181 +#define SRST_PERST_PCIE30X1 182 +#define SRST_CORE_RST_PCIE30X1 183 +#define SRST_NSTC_RST_PCIE30X1 184 +#define SRST_STC_RST_PCIE30X1 185 +#define SRST_PWR_RST_PCIE30X1 186 /* cru_softrst_con12 */ #define SRST_P_PCIE30X2 192 +#define SRST_PCIE30X2_POWERUP 193 +#define SRST_M_ARESET_PCIE30X2 194 +#define SRST_S_ARESET_PCIE30X2 195 +#define SRST_D_ARESET_PCIE30X2 196 +#define SRST_BRESET_PCIE30X2 197 +#define SRST_PERST_PCIE30X2 198 +#define SRST_CORE_RST_PCIE30X2 199 +#define SRST_NSTC_RST_PCIE30X2 200 +#define SRST_STC_RST_PCIE30X2 201 +#define SRST_PWR_RST_PCIE30X2 202 /* cru_softrst_con13 */ #define SRST_A_PHP_NIU 208 diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index 6c901930eb..d16e8755f6 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -15,5 +15,6 @@ #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 +#define PHY_TYPE_UFS 5 #endif /* _DT_BINDINGS_PHY */ diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h index 1dfc4f4fa7..1436e1d326 100644 --- a/include/dt-bindings/soc/rockchip,boot-mode.h +++ b/include/dt-bindings/soc/rockchip,boot-mode.h @@ -1,7 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ROCKCHIP_BOOT_MODE_H #define __ROCKCHIP_BOOT_MODE_H -/* high 24 bits is tag, low 8 bits is type */ +/*high 24 bits is tag, low 8 bits is type*/ #define REBOOT_FLAG 0x5242C300 /* normal boot */ #define BOOT_NORMAL (REBOOT_FLAG + 0) @@ -9,6 +10,10 @@ #define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) /* enter recovery */ #define BOOT_RECOVERY (REBOOT_FLAG + 3) +/* reboot by panic */ +#define BOOT_PANIC (REBOOT_FLAG + 7) +/* reboot by watchdog */ +#define BOOT_WATCHDOG (REBOOT_FLAG + 8) /* enter fastboot mode */ #define BOOT_FASTBOOT (REBOOT_FLAG + 9) /* enter charging mode */