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clk: rockchip: rk3128: support pclk_wdt get rate 

Change-Id: Ie5dbfe5bd3fdd7868a5db64b96471a5524bde462
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-04-09 17:36:21 +08:00
parent 68d8964cb4
commit 33a03efd7a
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/rockchip/clk_rk3128.c
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@ -237,6 +237,7 @@ static ulong rk3128_peri_get_clk(struct rk3128_clk_priv *priv, ulong clk_id)
case PCLK_I2C2:
case PCLK_I2C3:
case PCLK_PWM:
case PCLK_WDT:
con = readl(&cru->cru_clksel_con[10]);
div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT;
parent = rk3128_peri_get_clk(priv, ACLK_PERI);
@ -503,6 +504,7 @@ static ulong rk3128_clk_get_rate(struct clk *clk)
case PCLK_I2C2:
case PCLK_I2C3:
case PCLK_PWM:
case PCLK_WDT:
rate = rk3128_peri_get_clk(priv, clk->id);
break;
case ACLK_CPU: