rockchip: rk3308: coding style
Change-Id: If0404baf3019317e2dcf9a6c8a77e8a82a13f888 Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
This commit is contained in:
Zhihuan He
Jianhong Chen
parent
e9b1001b3c
commit
355cdcf345
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@ -196,6 +196,10 @@ struct rk3308_sgrf {
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check_member(rk3308_sgrf, fastboot_en, 0x20);
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enum {
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/* GPIO0B_IOMUX */
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GPIO0B_SEL_SHIFT = 0x0,
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GPIO0B_SEL_MASK = 0x3 << GPIO0B_SEL_SHIFT,
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/* GPIO1D_IOMUX */
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GPIO1D1_SEL_SHIFT = 2,
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GPIO1D1_SEL_MASK = 0x3 << GPIO1D1_SEL_SHIFT,
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@ -203,6 +207,31 @@ enum {
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GPIO1D0_SEL_SHIFT = 0,
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GPIO1D0_SEL_MASK = 0x3 << GPIO1D0_SEL_SHIFT,
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GPIO1D1_SEL_UART1_RX = 1,
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/* GPIO2A_IOMUX */
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GPIO2A1_SEL_SHIFT = 2,
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GPIO2A1_SEL_MASK = 0x3 << GPIO2A1_SEL_SHIFT,
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GPIO2A1_SEL_UART0_TX = 1,
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GPIO2A0_SEL_SHIFT = 0,
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GPIO2A0_SEL_MASK = 0x3 << GPIO2A0_SEL_SHIFT,
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GPIO2A0_SEL_UART0_RX = 1,
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/* GPIO3B_IOMUX */
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GPIO3B5_SEL_SHIFT = 12,
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GPIO3B5_SEL_MASK = 0xf << GPIO3B5_SEL_SHIFT,
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GPIO3B5_SEL_UART3_TX = 4,
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GPIO3B4_SEL_SHIFT = 8,
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GPIO3B4_SEL_MASK = 0xf << GPIO3B4_SEL_SHIFT,
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GPIO3B4_SEL_UART3_RX = 4,
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/* GPIO4B_IOMUX */
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GPIO4B1_SEL_SHIFT = 2,
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GPIO4B1_SEL_MASK = 0x3 << GPIO4B1_SEL_SHIFT,
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GPIO4B1_SEL_UART4_TX = 1,
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GPIO4B0_SEL_SHIFT = 0,
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GPIO4B0_SEL_MASK = 0x3 << GPIO4B0_SEL_SHIFT,
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GPIO4B0_SEL_UART4_RX = 1,
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/* GPIO4D_IOMUX */
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GPIO4D3_SEL_SHIFT = 6,
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GPIO4D3_SEL_MASK = 0x3 << GPIO4D3_SEL_SHIFT,
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@ -210,6 +239,23 @@ enum {
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GPIO4D2_SEL_SHIFT = 4,
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GPIO4D2_SEL_MASK = 0x3 << GPIO4D2_SEL_SHIFT,
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GPIO4D2_SEL_UART2_RXM1 = 2,
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/* PVTM_CON0 */
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PVTM_PMU_OSC_EN_SHIFT = 1,
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PVTM_PMU_OSC_EN_MASK = 0x1 << PVTM_PMU_OSC_EN_SHIFT,
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PVTM_PMU_OSC_EN = 1,
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PVTM_PMU_START_SHIFT = 0,
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PVTM_PMU_START_MASK = 0x1 << PVTM_PMU_START_SHIFT,
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PVTM_PMU_START = 1,
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/* PVTM_CON1 */
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PVTM_PMU_CAL_CNT = 0x1234,
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/* PVTM_STATUS0 */
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PVTM_PMU_FREQ_DONE_SHIFT = 0,
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PVTM_PMU_FREQ_DONE_MASK = 0x1 << PVTM_PMU_FREQ_DONE_SHIFT,
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/* UPCTL_CON0 */
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CYSYREQ_UPCTL_DDRSTDBY_SHIFT = 5,
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CYSYREQ_UPCTL_DDRSTDBY_MASK = 1 << CYSYREQ_UPCTL_DDRSTDBY_SHIFT,
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@ -217,10 +263,16 @@ enum {
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GRF_DDR_16BIT_EN_SHIFT = 0,
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GRF_DDR_16BIT_EN_MASK = 1 << GRF_DDR_16BIT_EN_SHIFT,
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GRF_DDR_16BIT_EN = 1,
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/* UPCTL_STATUS0 */
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DFI_SCRAMBLE_KEY_READY_SHIFT = 21,
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DFI_SCRAMBLE_KEY_READY_MASK = 0x1 << DFI_SCRAMBLE_KEY_READY_SHIFT,
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/* SOC_CON5 */
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UART2_MULTI_IOFUNC_SEL_SHIFT = 2,
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UART2_MULTI_IOFUNC_SEL_MASK = 0x3 << UART2_MULTI_IOFUNC_SEL_SHIFT,
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UART2_MULTI_IOFUNC_SEL_M1 = 1,
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/* SOC_CON12 */
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NOC_MSCH_MAIN_PARTIAL_SHIFT = 1,
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NOC_MSCH_MAIN_PARTIAL_MASK = 0x1 << NOC_MSCH_MAIN_PARTIAL_SHIFT,
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@ -231,4 +283,9 @@ enum {
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NOC_MSCH_MAINDDR3_DIS = 0,
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};
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enum { /* SGRF_CON0 */
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DDR_DFI_SCRAMBLE_EN_SHIFT = 13,
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DDR_DFI_SCRAMBLE_EN_MASK = 0x1 << DDR_DFI_SCRAMBLE_EN_SHIFT,
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DDR_DFI_SCRAMBLE_EN = 1,
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};
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#endif
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@ -68,4 +68,3 @@ enum { /* SFT_CON_LO */
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};
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#endif
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@ -134,4 +134,3 @@ void set_ds_odt(struct dram_info *priv,
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struct sdram_params *params_priv);
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#endif
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@ -20,7 +20,6 @@
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#define SDRAM_END_ADDR 0x80000000
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#define PATTERN (0x5aa5f00f)
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struct rv1108_service_msch {
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u32 id_coreid;
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u32 id_revisionid;
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@ -85,5 +84,4 @@ void set_bw_grf(struct dram_info *priv);
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void set_ds_odt(struct dram_info *priv,
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struct sdram_params *params_priv);
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#endif
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@ -14,17 +14,17 @@ struct ddr_pctl {
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u32 sctl;
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u32 stat;
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u32 intrstat;
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u32 reserved0[(0x40-0x10)/4];
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u32 reserved0[(0x40 - 0x10) / 4];
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u32 mcmd;
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u32 powctl;
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u32 powstat;
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u32 cmdtstat;
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u32 cmdtstaten;
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u32 reserved1[(0x60-0x54)/4];
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u32 reserved1[(0x60 - 0x54) / 4];
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u32 mrrcfg0;
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u32 mrrstat0;
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u32 mrrstat1;
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u32 reserved2[(0x7c-0x6c)/4];
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u32 reserved2[(0x7c - 0x6c) / 4];
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u32 mcfg1;
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u32 mcfg;
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u32 ppcfg;
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@ -39,7 +39,7 @@ struct ddr_pctl {
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u32 dtuprd2;
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u32 dtuprd3;
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u32 dtuawdt;
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u32 reserved4[(0xc0-0xb4)/4];
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u32 reserved4[(0xc0 - 0xb4) / 4];
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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@ -75,12 +75,12 @@ struct ddr_pctl {
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u32 tckesr;
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u32 tdpd;
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u32 trefi_mem_ddr3;
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u32 reserved5[(0x180-0x14c)/4];
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u32 reserved5[(0x180 - 0x14c) / 4];
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u32 ecccfg;
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u32 ecctst;
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u32 eccclr;
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u32 ecclog;
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u32 reserved6[(0x200-0x190)/4];
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u32 reserved6[(0x200 - 0x190) / 4];
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u32 dtuwactl;
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u32 dturactl;
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u32 dtucfg;
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@ -107,7 +107,7 @@ struct ddr_pctl {
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u32 reserved7;
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u32 dfitrddataen;
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u32 dfitphyrdlat;
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u32 reserved8[(0x270-0x268)/4];
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u32 reserved8[(0x270 - 0x268) / 4];
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u32 dfitphyupdtype0;
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u32 dfitphyupdtype1;
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u32 dfitphyupdtype2;
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@ -119,7 +119,7 @@ struct ddr_pctl {
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u32 dfiupdcfg;
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u32 dfitrefmski;
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u32 dfitctrlupdi;
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u32 reserved10[(0x2ac-0x29c)/4];
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u32 reserved10[(0x2ac - 0x29c) / 4];
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u32 dfitrcfg0;
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u32 dfitrstat0;
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u32 dfitrwrlvlen;
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@ -134,9 +134,9 @@ struct ddr_pctl {
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u32 dfistcfg2;
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u32 dfistparclr;
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u32 dfistparlog;
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u32 reserved12[(0x2f0-0x2e4)/4];
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u32 reserved12[(0x2f0 - 0x2e4) / 4];
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u32 dfilpcfg0;
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u32 reserved13[(0x300-0x2f4)/4];
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u32 reserved13[(0x300 - 0x2f4) / 4];
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u32 dfitrwrlvlresp0;
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u32 dfitrwrlvlresp1;
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u32 dfitrwrlvlresp2;
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@ -153,7 +153,7 @@ struct ddr_pctl {
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u32 dfitrrdlvlgatedelay1;
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u32 dfitrrdlvlgatedelay2;
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u32 dfitrcmd;
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u32 reserved14[(0x3f8-0x340)/4];
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u32 reserved14[(0x3f8 - 0x340) / 4];
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u32 ipvr;
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u32 iptr;
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};
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@ -565,7 +565,6 @@ enum {
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PD_IDLE_SHIFT = 8,
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TWO_T_SHIFT = 3,
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/* PCTL_MCFG1 */
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SR_IDLE_MASK = 0xff,
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HW_EXIT_IDLE_EN_SHIFT = 31,
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@ -236,7 +236,7 @@ config TPL_TEXT_BASE
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default 0xfff81000
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config TPL_MAX_SIZE
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default 12288
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default 10240
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config TPL_STACK
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default 0xfff84000
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@ -48,9 +48,7 @@ struct mm_region *mem_map = rk3308_mem_map;
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#define SGRF_BASE 0xff2b0000
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#define CRU_BASE 0xff500000
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enum {
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GPIO1C7_SHIFT = 8,
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GPIO1C7_MASK = GENMASK(11, 8),
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GPIO1C7_GPIO = 0,
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@ -209,17 +207,28 @@ int arch_cpu_init(void)
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static struct rk3308_grf * const grf = (void *)GRF_BASE;
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u32 glb_rst_st;
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/*
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* RK3308 internally default select 1.8v for VCCIO4 on reset state,
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* but some boards may give a 3.3V power supply for VCCIO4, this may
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* bring a risk of chip damage through overvoltage. So we internally
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* select 3.3V for VCCIO4 as early as possiple to reduces this risk.
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*/
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rk_clrsetreg(&grf->soc_con0, IOVSEL4_MASK, VCCIO4_3V3 << IOVSEL4_SHIFT);
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/*
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* write BOOT_WATCHDOG to boot mode register, if we are reset by wdt
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*/
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glb_rst_st = readl(&cru->glb_rst_st);
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writel(FST_GLB_WDT_RST | SND_GLB_WDT_RST, &cru->glb_rst_st);
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if (glb_rst_st & (FST_GLB_WDT_RST | SND_GLB_WDT_RST))
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writel(BOOT_WATCHDOG, CONFIG_ROCKCHIP_BOOT_MODE_REG);
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/* set wdt tsadc first global reset*/
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writel(WDT_GLB_SRST_CTRL << WDT_GLB_SRST_CTRL_SHIFT |
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TSADC_GLB_SRST_CTRL << TSADC_GLB_SRST_CTRL_SHIFT,
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&cru->glb_rst_con);
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/* Set qos priority level */
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writel(QOS_PRIORITY_P1_P0(1, 1),
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SERVICE_CPU_ADDR + DOS_PRIORITY_OFFSET);
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writel(QOS_PRIORITY_P1_P0(3, 3),
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