From 355cdcf34508d6ed289df7581f2c562b32e87d25 Mon Sep 17 00:00:00 2001 From: Zhihuan He Date: Wed, 23 Dec 2020 15:36:21 +0800 Subject: [PATCH] rockchip: rk3308: coding style Change-Id: If0404baf3019317e2dcf9a6c8a77e8a82a13f888 Signed-off-by: Zhihuan He --- .../include/asm/arch-rockchip/grf_rk3308.h | 57 +++++++++++++++++++ .../include/asm/arch-rockchip/pmu_rk3308.h | 1 - .../include/asm/arch-rockchip/sdram_rk3308.h | 1 - .../include/asm/arch-rockchip/sdram_rv1108.h | 2 - .../asm/arch-rockchip/sdram_rv1108_pctl_phy.h | 23 ++++---- arch/arm/mach-rockchip/Kconfig | 2 +- arch/arm/mach-rockchip/rk3308/rk3308.c | 13 ++++- 7 files changed, 80 insertions(+), 19 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3308.h b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h index 2d0663f4db..0ee72b7666 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3308.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h @@ -196,6 +196,10 @@ struct rk3308_sgrf { check_member(rk3308_sgrf, fastboot_en, 0x20); enum { + /* GPIO0B_IOMUX */ + GPIO0B_SEL_SHIFT = 0x0, + GPIO0B_SEL_MASK = 0x3 << GPIO0B_SEL_SHIFT, + /* GPIO1D_IOMUX */ GPIO1D1_SEL_SHIFT = 2, GPIO1D1_SEL_MASK = 0x3 << GPIO1D1_SEL_SHIFT, @@ -203,6 +207,31 @@ enum { GPIO1D0_SEL_SHIFT = 0, GPIO1D0_SEL_MASK = 0x3 << GPIO1D0_SEL_SHIFT, GPIO1D1_SEL_UART1_RX = 1, + + /* GPIO2A_IOMUX */ + GPIO2A1_SEL_SHIFT = 2, + GPIO2A1_SEL_MASK = 0x3 << GPIO2A1_SEL_SHIFT, + GPIO2A1_SEL_UART0_TX = 1, + GPIO2A0_SEL_SHIFT = 0, + GPIO2A0_SEL_MASK = 0x3 << GPIO2A0_SEL_SHIFT, + GPIO2A0_SEL_UART0_RX = 1, + + /* GPIO3B_IOMUX */ + GPIO3B5_SEL_SHIFT = 12, + GPIO3B5_SEL_MASK = 0xf << GPIO3B5_SEL_SHIFT, + GPIO3B5_SEL_UART3_TX = 4, + GPIO3B4_SEL_SHIFT = 8, + GPIO3B4_SEL_MASK = 0xf << GPIO3B4_SEL_SHIFT, + GPIO3B4_SEL_UART3_RX = 4, + + /* GPIO4B_IOMUX */ + GPIO4B1_SEL_SHIFT = 2, + GPIO4B1_SEL_MASK = 0x3 << GPIO4B1_SEL_SHIFT, + GPIO4B1_SEL_UART4_TX = 1, + GPIO4B0_SEL_SHIFT = 0, + GPIO4B0_SEL_MASK = 0x3 << GPIO4B0_SEL_SHIFT, + GPIO4B0_SEL_UART4_RX = 1, + /* GPIO4D_IOMUX */ GPIO4D3_SEL_SHIFT = 6, GPIO4D3_SEL_MASK = 0x3 << GPIO4D3_SEL_SHIFT, @@ -210,6 +239,23 @@ enum { GPIO4D2_SEL_SHIFT = 4, GPIO4D2_SEL_MASK = 0x3 << GPIO4D2_SEL_SHIFT, GPIO4D2_SEL_UART2_RXM1 = 2, + + /* PVTM_CON0 */ + PVTM_PMU_OSC_EN_SHIFT = 1, + PVTM_PMU_OSC_EN_MASK = 0x1 << PVTM_PMU_OSC_EN_SHIFT, + PVTM_PMU_OSC_EN = 1, + + PVTM_PMU_START_SHIFT = 0, + PVTM_PMU_START_MASK = 0x1 << PVTM_PMU_START_SHIFT, + PVTM_PMU_START = 1, + + /* PVTM_CON1 */ + PVTM_PMU_CAL_CNT = 0x1234, + + /* PVTM_STATUS0 */ + PVTM_PMU_FREQ_DONE_SHIFT = 0, + PVTM_PMU_FREQ_DONE_MASK = 0x1 << PVTM_PMU_FREQ_DONE_SHIFT, + /* UPCTL_CON0 */ CYSYREQ_UPCTL_DDRSTDBY_SHIFT = 5, CYSYREQ_UPCTL_DDRSTDBY_MASK = 1 << CYSYREQ_UPCTL_DDRSTDBY_SHIFT, @@ -217,10 +263,16 @@ enum { GRF_DDR_16BIT_EN_SHIFT = 0, GRF_DDR_16BIT_EN_MASK = 1 << GRF_DDR_16BIT_EN_SHIFT, GRF_DDR_16BIT_EN = 1, + + /* UPCTL_STATUS0 */ + DFI_SCRAMBLE_KEY_READY_SHIFT = 21, + DFI_SCRAMBLE_KEY_READY_MASK = 0x1 << DFI_SCRAMBLE_KEY_READY_SHIFT, + /* SOC_CON5 */ UART2_MULTI_IOFUNC_SEL_SHIFT = 2, UART2_MULTI_IOFUNC_SEL_MASK = 0x3 << UART2_MULTI_IOFUNC_SEL_SHIFT, UART2_MULTI_IOFUNC_SEL_M1 = 1, + /* SOC_CON12 */ NOC_MSCH_MAIN_PARTIAL_SHIFT = 1, NOC_MSCH_MAIN_PARTIAL_MASK = 0x1 << NOC_MSCH_MAIN_PARTIAL_SHIFT, @@ -231,4 +283,9 @@ enum { NOC_MSCH_MAINDDR3_DIS = 0, }; +enum { /* SGRF_CON0 */ + DDR_DFI_SCRAMBLE_EN_SHIFT = 13, + DDR_DFI_SCRAMBLE_EN_MASK = 0x1 << DDR_DFI_SCRAMBLE_EN_SHIFT, + DDR_DFI_SCRAMBLE_EN = 1, +}; #endif diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3308.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3308.h index 6c25ec065c..5714f1f45d 100644 --- a/arch/arm/include/asm/arch-rockchip/pmu_rk3308.h +++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3308.h @@ -68,4 +68,3 @@ enum { /* SFT_CON_LO */ }; #endif - diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3308.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3308.h index d215bb2f0f..30034b980f 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3308.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3308.h @@ -134,4 +134,3 @@ void set_ds_odt(struct dram_info *priv, struct sdram_params *params_priv); #endif - diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rv1108.h b/arch/arm/include/asm/arch-rockchip/sdram_rv1108.h index b6947523cb..961fedb8b5 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rv1108.h @@ -20,7 +20,6 @@ #define SDRAM_END_ADDR 0x80000000 #define PATTERN (0x5aa5f00f) - struct rv1108_service_msch { u32 id_coreid; u32 id_revisionid; @@ -85,5 +84,4 @@ void set_bw_grf(struct dram_info *priv); void set_ds_odt(struct dram_info *priv, struct sdram_params *params_priv); - #endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rv1108_pctl_phy.h b/arch/arm/include/asm/arch-rockchip/sdram_rv1108_pctl_phy.h index b7bb61921b..f0b10d94eb 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rv1108_pctl_phy.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rv1108_pctl_phy.h @@ -14,17 +14,17 @@ struct ddr_pctl { u32 sctl; u32 stat; u32 intrstat; - u32 reserved0[(0x40-0x10)/4]; + u32 reserved0[(0x40 - 0x10) / 4]; u32 mcmd; u32 powctl; u32 powstat; u32 cmdtstat; u32 cmdtstaten; - u32 reserved1[(0x60-0x54)/4]; + u32 reserved1[(0x60 - 0x54) / 4]; u32 mrrcfg0; u32 mrrstat0; u32 mrrstat1; - u32 reserved2[(0x7c-0x6c)/4]; + u32 reserved2[(0x7c - 0x6c) / 4]; u32 mcfg1; u32 mcfg; u32 ppcfg; @@ -39,7 +39,7 @@ struct ddr_pctl { u32 dtuprd2; u32 dtuprd3; u32 dtuawdt; - u32 reserved4[(0xc0-0xb4)/4]; + u32 reserved4[(0xc0 - 0xb4) / 4]; u32 togcnt1u; u32 tinit; u32 trsth; @@ -75,12 +75,12 @@ struct ddr_pctl { u32 tckesr; u32 tdpd; u32 trefi_mem_ddr3; - u32 reserved5[(0x180-0x14c)/4]; + u32 reserved5[(0x180 - 0x14c) / 4]; u32 ecccfg; u32 ecctst; u32 eccclr; u32 ecclog; - u32 reserved6[(0x200-0x190)/4]; + u32 reserved6[(0x200 - 0x190) / 4]; u32 dtuwactl; u32 dturactl; u32 dtucfg; @@ -107,7 +107,7 @@ struct ddr_pctl { u32 reserved7; u32 dfitrddataen; u32 dfitphyrdlat; - u32 reserved8[(0x270-0x268)/4]; + u32 reserved8[(0x270 - 0x268) / 4]; u32 dfitphyupdtype0; u32 dfitphyupdtype1; u32 dfitphyupdtype2; @@ -119,7 +119,7 @@ struct ddr_pctl { u32 dfiupdcfg; u32 dfitrefmski; u32 dfitctrlupdi; - u32 reserved10[(0x2ac-0x29c)/4]; + u32 reserved10[(0x2ac - 0x29c) / 4]; u32 dfitrcfg0; u32 dfitrstat0; u32 dfitrwrlvlen; @@ -134,9 +134,9 @@ struct ddr_pctl { u32 dfistcfg2; u32 dfistparclr; u32 dfistparlog; - u32 reserved12[(0x2f0-0x2e4)/4]; + u32 reserved12[(0x2f0 - 0x2e4) / 4]; u32 dfilpcfg0; - u32 reserved13[(0x300-0x2f4)/4]; + u32 reserved13[(0x300 - 0x2f4) / 4]; u32 dfitrwrlvlresp0; u32 dfitrwrlvlresp1; u32 dfitrwrlvlresp2; @@ -153,7 +153,7 @@ struct ddr_pctl { u32 dfitrrdlvlgatedelay1; u32 dfitrrdlvlgatedelay2; u32 dfitrcmd; - u32 reserved14[(0x3f8-0x340)/4]; + u32 reserved14[(0x3f8 - 0x340) / 4]; u32 ipvr; u32 iptr; }; @@ -565,7 +565,6 @@ enum { PD_IDLE_SHIFT = 8, TWO_T_SHIFT = 3, - /* PCTL_MCFG1 */ SR_IDLE_MASK = 0xff, HW_EXIT_IDLE_EN_SHIFT = 31, diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 88628cb435..3a0ba456fd 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -236,7 +236,7 @@ config TPL_TEXT_BASE default 0xfff81000 config TPL_MAX_SIZE - default 12288 + default 10240 config TPL_STACK default 0xfff84000 diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index f259fd8f83..49f3490396 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -48,9 +48,7 @@ struct mm_region *mem_map = rk3308_mem_map; #define SGRF_BASE 0xff2b0000 #define CRU_BASE 0xff500000 - enum { - GPIO1C7_SHIFT = 8, GPIO1C7_MASK = GENMASK(11, 8), GPIO1C7_GPIO = 0, @@ -209,17 +207,28 @@ int arch_cpu_init(void) static struct rk3308_grf * const grf = (void *)GRF_BASE; u32 glb_rst_st; + /* + * RK3308 internally default select 1.8v for VCCIO4 on reset state, + * but some boards may give a 3.3V power supply for VCCIO4, this may + * bring a risk of chip damage through overvoltage. So we internally + * select 3.3V for VCCIO4 as early as possiple to reduces this risk. + */ rk_clrsetreg(&grf->soc_con0, IOVSEL4_MASK, VCCIO4_3V3 << IOVSEL4_SHIFT); + /* + * write BOOT_WATCHDOG to boot mode register, if we are reset by wdt + */ glb_rst_st = readl(&cru->glb_rst_st); writel(FST_GLB_WDT_RST | SND_GLB_WDT_RST, &cru->glb_rst_st); if (glb_rst_st & (FST_GLB_WDT_RST | SND_GLB_WDT_RST)) writel(BOOT_WATCHDOG, CONFIG_ROCKCHIP_BOOT_MODE_REG); + /* set wdt tsadc first global reset*/ writel(WDT_GLB_SRST_CTRL << WDT_GLB_SRST_CTRL_SHIFT | TSADC_GLB_SRST_CTRL << TSADC_GLB_SRST_CTRL_SHIFT, &cru->glb_rst_con); + /* Set qos priority level */ writel(QOS_PRIORITY_P1_P0(1, 1), SERVICE_CPU_ADDR + DOS_PRIORITY_OFFSET); writel(QOS_PRIORITY_P1_P0(3, 3),