rockchip: rk3308: coding style

Change-Id: If0404baf3019317e2dcf9a6c8a77e8a82a13f888
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

arch/arm/include/asm/arch-rockchip/grf_rk3308.h

@@ -196,6 +196,10 @@ struct rk3308_sgrf {
 check_member(rk3308_sgrf, fastboot_en, 0x20);
 
 enum {
+	/* GPIO0B_IOMUX */
+	GPIO0B_SEL_SHIFT		= 0x0,
+	GPIO0B_SEL_MASK			= 0x3 << GPIO0B_SEL_SHIFT,
+
 	/* GPIO1D_IOMUX */
 	GPIO1D1_SEL_SHIFT		= 2,
 	GPIO1D1_SEL_MASK		= 0x3 << GPIO1D1_SEL_SHIFT,
@@ -203,6 +207,31 @@ enum {
 	GPIO1D0_SEL_SHIFT		= 0,
 	GPIO1D0_SEL_MASK		= 0x3 << GPIO1D0_SEL_SHIFT,
 	GPIO1D1_SEL_UART1_RX		= 1,
+
+	/* GPIO2A_IOMUX */
+	GPIO2A1_SEL_SHIFT		= 2,
+	GPIO2A1_SEL_MASK		= 0x3 << GPIO2A1_SEL_SHIFT,
+	GPIO2A1_SEL_UART0_TX		= 1,
+	GPIO2A0_SEL_SHIFT		= 0,
+	GPIO2A0_SEL_MASK		= 0x3 << GPIO2A0_SEL_SHIFT,
+	GPIO2A0_SEL_UART0_RX		= 1,
+
+	/* GPIO3B_IOMUX */
+	GPIO3B5_SEL_SHIFT		= 12,
+	GPIO3B5_SEL_MASK		= 0xf << GPIO3B5_SEL_SHIFT,
+	GPIO3B5_SEL_UART3_TX		= 4,
+	GPIO3B4_SEL_SHIFT		= 8,
+	GPIO3B4_SEL_MASK		= 0xf << GPIO3B4_SEL_SHIFT,
+	GPIO3B4_SEL_UART3_RX		= 4,
+
+	/* GPIO4B_IOMUX */
+	GPIO4B1_SEL_SHIFT		= 2,
+	GPIO4B1_SEL_MASK		= 0x3 << GPIO4B1_SEL_SHIFT,
+	GPIO4B1_SEL_UART4_TX		= 1,
+	GPIO4B0_SEL_SHIFT		= 0,
+	GPIO4B0_SEL_MASK		= 0x3 << GPIO4B0_SEL_SHIFT,
+	GPIO4B0_SEL_UART4_RX		= 1,
+
 	/* GPIO4D_IOMUX */
 	GPIO4D3_SEL_SHIFT		= 6,
 	GPIO4D3_SEL_MASK		= 0x3 << GPIO4D3_SEL_SHIFT,
@@ -210,6 +239,23 @@ enum {
 	GPIO4D2_SEL_SHIFT		= 4,
 	GPIO4D2_SEL_MASK		= 0x3 << GPIO4D2_SEL_SHIFT,
 	GPIO4D2_SEL_UART2_RXM1		= 2,
+
+	/* PVTM_CON0 */
+	PVTM_PMU_OSC_EN_SHIFT		= 1,
+	PVTM_PMU_OSC_EN_MASK		= 0x1 << PVTM_PMU_OSC_EN_SHIFT,
+	PVTM_PMU_OSC_EN			= 1,
+
+	PVTM_PMU_START_SHIFT		= 0,
+	PVTM_PMU_START_MASK		= 0x1 << PVTM_PMU_START_SHIFT,
+	PVTM_PMU_START			= 1,
+
+	/* PVTM_CON1 */
+	PVTM_PMU_CAL_CNT		= 0x1234,
+
+	/* PVTM_STATUS0 */
+	PVTM_PMU_FREQ_DONE_SHIFT	= 0,
+	PVTM_PMU_FREQ_DONE_MASK		= 0x1 << PVTM_PMU_FREQ_DONE_SHIFT,
+
 	/* UPCTL_CON0 */
 	CYSYREQ_UPCTL_DDRSTDBY_SHIFT	= 5,
 	CYSYREQ_UPCTL_DDRSTDBY_MASK	= 1 << CYSYREQ_UPCTL_DDRSTDBY_SHIFT,
@@ -217,10 +263,16 @@ enum {
 	GRF_DDR_16BIT_EN_SHIFT		= 0,
 	GRF_DDR_16BIT_EN_MASK		= 1 << GRF_DDR_16BIT_EN_SHIFT,
 	GRF_DDR_16BIT_EN		= 1,
+
+	/* UPCTL_STATUS0 */
+	DFI_SCRAMBLE_KEY_READY_SHIFT	= 21,
+	DFI_SCRAMBLE_KEY_READY_MASK	= 0x1 << DFI_SCRAMBLE_KEY_READY_SHIFT,
+
 	/* SOC_CON5 */
 	UART2_MULTI_IOFUNC_SEL_SHIFT	= 2,
 	UART2_MULTI_IOFUNC_SEL_MASK	= 0x3 << UART2_MULTI_IOFUNC_SEL_SHIFT,
 	UART2_MULTI_IOFUNC_SEL_M1	= 1,
+
 	/* SOC_CON12 */
 	NOC_MSCH_MAIN_PARTIAL_SHIFT	= 1,
 	NOC_MSCH_MAIN_PARTIAL_MASK	= 0x1 << NOC_MSCH_MAIN_PARTIAL_SHIFT,
@@ -231,4 +283,9 @@ enum {
 	NOC_MSCH_MAINDDR3_DIS		= 0,
 };
 
+enum { /* SGRF_CON0 */
+	DDR_DFI_SCRAMBLE_EN_SHIFT	= 13,
+	DDR_DFI_SCRAMBLE_EN_MASK	= 0x1 << DDR_DFI_SCRAMBLE_EN_SHIFT,
+	DDR_DFI_SCRAMBLE_EN		= 1,
+};
 #endif

arch/arm/include/asm/arch-rockchip/pmu_rk3308.h

@@ -68,4 +68,3 @@ enum { /* SFT_CON_LO */
 };
 
 #endif
-

arch/arm/include/asm/arch-rockchip/sdram_rk3308.h

@@ -134,4 +134,3 @@ void set_ds_odt(struct dram_info *priv,
 		struct sdram_params *params_priv);
 
 #endif
-

arch/arm/include/asm/arch-rockchip/sdram_rv1108.h

@@ -20,7 +20,6 @@
 #define SDRAM_END_ADDR		0x80000000
 #define PATTERN			(0x5aa5f00f)
 
-
 struct rv1108_service_msch {
 	u32 id_coreid;
 	u32 id_revisionid;
@@ -85,5 +84,4 @@ void set_bw_grf(struct dram_info *priv);
 void set_ds_odt(struct dram_info *priv,
 		struct sdram_params *params_priv);
 
-
 #endif

arch/arm/include/asm/arch-rockchip/sdram_rv1108_pctl_phy.h

@@ -565,7 +565,6 @@ enum {
 	PD_IDLE_SHIFT				= 8,
 	TWO_T_SHIFT				= 3,
 
-
 	/* PCTL_MCFG1 */
 	SR_IDLE_MASK				= 0xff,
 	HW_EXIT_IDLE_EN_SHIFT			= 31,

arch/arm/mach-rockchip/Kconfig

@@ -236,7 +236,7 @@ config TPL_TEXT_BASE
 	default 0xfff81000
 
 config TPL_MAX_SIZE
-	default 12288
+	default 10240
 
 config TPL_STACK
 	default 0xfff84000

arch/arm/mach-rockchip/rk3308/rk3308.c

@@ -48,9 +48,7 @@ struct mm_region *mem_map = rk3308_mem_map;
 #define SGRF_BASE	0xff2b0000
 #define CRU_BASE	0xff500000
 
-
 enum {
-
 	GPIO1C7_SHIFT		= 8,
 	GPIO1C7_MASK		= GENMASK(11, 8),
 	GPIO1C7_GPIO		= 0,
@@ -209,17 +207,28 @@ int arch_cpu_init(void)
 	static struct rk3308_grf * const grf = (void *)GRF_BASE;
 	u32 glb_rst_st;
 
+	/*
+	 * RK3308 internally default select 1.8v for VCCIO4 on reset state,
+	 * but some boards may give a 3.3V power supply for VCCIO4, this may
+	 * bring a risk of chip damage through overvoltage. So we internally
+	 * select 3.3V for VCCIO4 as early as possiple to reduces this risk.
+	 */
 	rk_clrsetreg(&grf->soc_con0, IOVSEL4_MASK, VCCIO4_3V3 << IOVSEL4_SHIFT);
 
+	/*
+	 * write BOOT_WATCHDOG to boot mode register, if we are reset by wdt
+	 */
 	glb_rst_st = readl(&cru->glb_rst_st);
 	writel(FST_GLB_WDT_RST | SND_GLB_WDT_RST, &cru->glb_rst_st);
 	if (glb_rst_st & (FST_GLB_WDT_RST | SND_GLB_WDT_RST))
 		writel(BOOT_WATCHDOG, CONFIG_ROCKCHIP_BOOT_MODE_REG);
 
+	/* set wdt tsadc first global reset*/
 	writel(WDT_GLB_SRST_CTRL << WDT_GLB_SRST_CTRL_SHIFT |
 	       TSADC_GLB_SRST_CTRL << TSADC_GLB_SRST_CTRL_SHIFT,
 	       &cru->glb_rst_con);
 
+	/* Set qos priority level */
 	writel(QOS_PRIORITY_P1_P0(1, 1),
 	       SERVICE_CPU_ADDR + DOS_PRIORITY_OFFSET);
 	writel(QOS_PRIORITY_P1_P0(3, 3),