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usb: dwc3: do not use 3.0 clock when operating in 2.0 mode 

In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.

Change-Id: Ib93da14b5309ec094b952e03f8514817910fedfa
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu 2020-11-13 18:17:26 +08:00 committed by Jianhong Chen
parent cce972667a
commit 3b2dd5de37
2 changed files with 13 additions and 0 deletions
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10
drivers/usb/dwc3/core.c
View File

@ -490,6 +490,16 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (ret) if (ret)
goto err0; goto err0;
if (dwc->revision >= DWC3_REVISION_250A) {
reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
if (dwc->maximum_speed == USB_SPEED_HIGH ||
dwc->maximum_speed == USB_SPEED_FULL)
reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
}
reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_SCALEDOWN_MASK; reg &= ~DWC3_GCTL_SCALEDOWN_MASK;

3
drivers/usb/dwc3/core.h
View File

@ -162,6 +162,9 @@
#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
/* Global User Control 1 Register */
#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
/* Global USB2 PHY Configuration Register */ /* Global USB2 PHY Configuration Register */
#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)