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Merge git://git.denx.de/u-boot-fsl-qoriq

This commit is contained in:
Tom Rini 2017-04-18 11:36:06 -04:00
parent 9481f186d0 e0dfec863e
commit 3c476d841d
82 changed files with 740 additions and 172 deletions
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2
arch/arm/cpu/armv7/Makefile
View File

@ -12,7 +12,7 @@ obj-y += cache_v7.o cache_v7_asm.o
obj-y += cpu.o cp15.o obj-y += cpu.o cp15.o
obj-y += syslib.o obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_LS102XA),) ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_ARCH_LS1021A),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o obj-y += lowlevel_init.o
endif endif

23
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -36,6 +36,7 @@ config ARCH_LS1046A
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008336
select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009801
select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A009942
@ -63,6 +64,8 @@ config ARCH_LS2080A
select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_2 select SYS_FSL_SRDS_2
select FSL_TZASC_1
select FSL_TZASC_2
select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008336
select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008514 select SYS_FSL_ERRATUM_A008514
@ -171,6 +174,20 @@ config SYS_LS_PPA_FW_ADDR
QSPI flash, this address is a directly memory-mapped. QSPI flash, this address is a directly memory-mapped.
If it is in a serial accessed flash, such as NAND and SD If it is in a serial accessed flash, such as NAND and SD
card, it is a byte offset. card, it is a byte offset.
config SYS_LS_PPA_ESBC_ADDR
hex "hdr address of PPA firmware loading from"
depends on FSL_LS_PPA && CHAIN_OF_TRUST
default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
help
If the PPA header firmware locate at XIP flash, such as NOR or
QSPI flash, this address is a directly memory-mapped.
If it is in a serial accessed flash, such as NAND and SD
card, it is a byte offset.
endmenu endmenu
config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A010315
@ -223,6 +240,12 @@ config SYS_FSL_SRDS_2
config SYS_HAS_SERDES config SYS_HAS_SERDES
bool bool
config FSL_TZASC_1
bool
config FSL_TZASC_2
bool
endmenu endmenu
menu "Layerscape clock tree configuration" menu "Layerscape clock tree configuration"

4
arch/arm/cpu/armv8/fsl-layerscape/Makefile
View File

@ -22,11 +22,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
endif endif
endif endif
ifneq ($(CONFIG_LS2080A),) ifneq ($(CONFIG_ARCH_LS2080A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
endif endif
ifneq ($(CONFIG_LS1043A),) ifneq ($(CONFIG_ARCH_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
endif endif

6
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -92,7 +92,7 @@ static inline void early_mmu_setup(void)
static void fix_pcie_mmu_map(void) static void fix_pcie_mmu_map(void)
{ {
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
unsigned int i; unsigned int i;
u32 svr, ver; u32 svr, ver;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@ -523,7 +523,7 @@ int timer_init(void)
#ifdef CONFIG_FSL_LSCH3 #ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif #endif
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id; u32 svr_dev_id;
#endif #endif
@ -541,7 +541,7 @@ int timer_init(void)
out_le32(cltbenr, 0xf); out_le32(cltbenr, 0xf);
#endif #endif
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
/* /*
* In certain Layerscape SoCs, the clock for each core's * In certain Layerscape SoCs, the clock for each core's
* has an enable bit in the PMU Physical Core Time Base Enable * has an enable bit in the PMU Physical Core Time Base Enable

4
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
View File

@ -373,8 +373,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1); "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif #endif
do_fixup_by_compat_u32(blob, "fixed-clock", do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1); CONFIG_SYS_CLK_FREQ, 1);
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
ft_pci_setup(blob, bd); ft_pci_setup(blob, bd);

26
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View File

@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
#ifdef CONFIG_FSL_LSCH3 #ifdef CONFIG_FSL_LSCH3
/* Set Wuo bit for RN-I 20 */ /* Set Wuo bit for RN-I 20 */
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
ldr x0, =CCI_AUX_CONTROL_BASE(20) ldr x0, =CCI_AUX_CONTROL_BASE(20)
ldr x1, =0x00000010 ldr x1, =0x00000010
bl ccn504_set_aux bl ccn504_set_aux
@ -229,38 +229,40 @@ ENTRY(lowlevel_init)
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
* placeholders. * placeholders.
*/ */
#ifdef CONFIG_FSL_TZASC_1
ldr x1, =TZASC_GATE_KEEPER(0) ldr x1, =TZASC_GATE_KEEPER(0)
ldr w0, [x1] /* Filter 0 Gate Keeper Register */ ldr w0, [x1] /* Filter 0 Gate Keeper Register */
orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
str w0, [x1] str w0, [x1]
ldr x1, =TZASC_GATE_KEEPER(1)
ldr w0, [x1] /* Filter 0 Gate Keeper Register */
orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
str w0, [x1]
ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
ldr w0, [x1] /* Region-0 Attributes Register */ ldr w0, [x1] /* Region-0 Attributes Register */
orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
str w0, [x1] str w0, [x1]
ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
ldr w0, [x1] /* Region-0 Access Register */
mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
str w0, [x1]
#endif
#ifdef CONFIG_FSL_TZASC_2
ldr x1, =TZASC_GATE_KEEPER(1)
ldr w0, [x1] /* Filter 0 Gate Keeper Register */
orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
str w0, [x1]
ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
ldr w0, [x1] /* Region-1 Attributes Register */ ldr w0, [x1] /* Region-1 Attributes Register */
orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
str w0, [x1] str w0, [x1]
ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
ldr w0, [x1] /* Region-0 Access Register */
mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
str w0, [x1]
ldr x1, =TZASC_REGION_ID_ACCESS_0(1) ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
ldr w0, [x1] /* Region-1 Attributes Register */ ldr w0, [x1] /* Region-1 Attributes Register */
mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
str w0, [x1] str w0, [x1]
#endif
isb isb
dsb sy dsb sy
#endif #endif

1
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
View File

@ -70,6 +70,7 @@ static struct serdes_config serdes2_cfg_tbl[] = {
SATA2 } }, SATA2 } },
{0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
SATA2 } }, SATA2 } },
{0x51, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
{0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } }, {0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } },
{} {}
}; };

2
arch/arm/cpu/armv8/fsl-layerscape/ppa.c
View File

@ -178,7 +178,7 @@ int ppa_init(void)
ppa_img_addr = (uintptr_t)ppa_fit_addr; ppa_img_addr = (uintptr_t)ppa_fit_addr;
if (fsl_check_boot_mode_secure() != 0) { if (fsl_check_boot_mode_secure() != 0) {
ret = fsl_secboot_validate(ppa_esbc_hdr, ret = fsl_secboot_validate(ppa_esbc_hdr,
CONFIG_PPA_KEY_HASH, PPA_KEY_HASH,
&ppa_img_addr); &ppa_img_addr);
if (ret != 0) if (ret != 0)
printf("PPA validation failed\n"); printf("PPA validation failed\n");

20
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View File

@ -41,13 +41,31 @@ u32 spl_boot_mode(const u32 boot_device)
} }
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2)
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
* SMMU must be reset in bypass mode.
* Set the ClientPD bit and Clear the USFCFG Bit
*/
u32 val;
val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_SCR0, val);
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
}
void board_init_f(ulong dummy) void board_init_f(ulong dummy)
{ {
/* Clear global data */ /* Clear global data */
memset((void *)gd, 0, sizeof(gd_t)); memset((void *)gd, 0, sizeof(gd_t));
board_early_init_f(); board_early_init_f();
timer_init(); timer_init();
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
env_init(); env_init();
#endif #endif
get_clocks(); get_clocks();

2
arch/arm/dts/Makefile
View File

@ -166,7 +166,7 @@ dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
am571x-idk.dtb am571x-idk.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \ ls1021a-qds-lpuart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb ls1021a-iot-duart.dtb

13
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -18,7 +18,7 @@
*/ */
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8 #define SRDS_MAX_LANES 8
#define CONFIG_SYS_PAGE_SIZE 0x10000 #define CONFIG_SYS_PAGE_SIZE 0x10000
@ -132,7 +132,7 @@
#define CONFIG_SYS_FSL_PEX_LUT_BE #define CONFIG_SYS_FSL_PEX_LUT_BE
/* SoC related */ /* SoC related */
#ifdef CONFIG_LS1043A #ifdef CONFIG_ARCH_LS1043A
#define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_DTSEC 7
@ -185,7 +185,12 @@
#elif defined(CONFIG_ARCH_LS1012A) #elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000 #define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000 #define GICC_BASE 0x01402000
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SEC_MON_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define CONFIG_KEY_REVOCATION
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
@ -199,7 +204,7 @@
#define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SNVS_LE #define CONFIG_SYS_FSL_SEC_MON_BE
#define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE #define CONFIG_SYS_FSL_SRK_LE
#define CONFIG_KEY_REVOCATION #define CONFIG_KEY_REVOCATION

2
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
View File

@ -249,7 +249,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE, CONFIG_SYS_PCIE4_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |

2
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
View File

@ -9,7 +9,7 @@
#include <config.h> #include <config.h>
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
enum srds_prtcl { enum srds_prtcl {
/* /*
* Nobody will check whether the device 'NONE' has been configured, * Nobody will check whether the device 'NONE' has been configured,

2
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -108,7 +108,7 @@
#define DCU_LAYER_MAX_NUM 16 #define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else #else

2
arch/arm/include/asm/config.h
View File

@ -14,7 +14,7 @@
#define CONFIG_STATIC_RELA #define CONFIG_STATIC_RELA
#endif #endif
#if defined(CONFIG_LS102XA) || \ #if defined(CONFIG_ARCH_LS1021A) || \
defined(CONFIG_CPU_PXA27X) || \ defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS) || \ defined(CONFIG_CPU_MONAHANS) || \
defined(CONFIG_CPU_PXA25X) || \ defined(CONFIG_CPU_PXA25X) || \

53
arch/arm/include/asm/fsl_secure_boot.h
View File

@ -27,10 +27,11 @@
#define CONFIG_SPL_UBOOT_KEY_HASH NULL #define CONFIG_SPL_UBOOT_KEY_HASH NULL
#endif /* ifdef CONFIG_SPL_BUILD */ #endif /* ifdef CONFIG_SPL_BUILD */
#define CONFIG_KEY_REVOCATION
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD
#define CONFIG_CMD_BLOB #define CONFIG_CMD_BLOB
#define CONFIG_CMD_HASH #define CONFIG_CMD_HASH
#define CONFIG_KEY_REVOCATION
#ifndef CONFIG_SYS_RAMBOOT #ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images /* The key used for verification of next level images
* is picked up from an Extension Table which has * is picked up from an Extension Table which has
@ -46,14 +47,15 @@
#endif #endif
#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) #if defined(CONFIG_FSL_LAYERSCAPE)
/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit /*
* Similiarly for LS2080 * For fsl layerscape based platforms, ESBC image Address in Header
* is 64 bit.
*/ */
#define CONFIG_ESBC_ADDR_64BIT #define CONFIG_ESBC_ADDR_64BIT
#endif #endif
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
#define CONFIG_EXTRA_ENV \ #define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xa0000000;" \ "setenv fdt_high 0xa0000000;" \
"setenv initrd_high 0xcfffffff;" \ "setenv initrd_high 0xcfffffff;" \
@ -68,7 +70,7 @@
/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
* Non-XIP Memory (Nand/SD)*/ * Non-XIP Memory (Nand/SD)*/
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \
defined(CONFIG_SD_BOOT) defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT)
#define CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BOOTSCRIPT_COPY_RAM
#endif #endif
/* The address needs to be modified according to NOR, NAND, SD and /* The address needs to be modified according to NOR, NAND, SD and
@ -86,16 +88,37 @@
/* For SD boot address and size are assigned in terms of sector /* For SD boot address and size are assigned in terms of sector
* offset and no. of sectors respectively. * offset and no. of sectors respectively.
*/ */
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920
#else
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900
#endif
#define CONFIG_BS_ADDR_DEVICE 0x00000940 #define CONFIG_BS_ADDR_DEVICE 0x00000940
#define CONFIG_BS_HDR_SIZE 0x00000010 #define CONFIG_BS_HDR_SIZE 0x00000010
#define CONFIG_BS_SIZE 0x00000008 #define CONFIG_BS_SIZE 0x00000008
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
#define CONFIG_BS_ADDR_DEVICE 0x00802000
#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BS_SIZE 0x00001000
#elif defined(CONFIG_QSPI_BOOT)
#ifdef CONFIG_ARCH_LS1046A
#define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000
#define CONFIG_BS_ADDR_DEVICE 0x40800000
#elif defined(CONFIG_ARCH_LS1012A)
#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000
#define CONFIG_BS_ADDR_DEVICE 0x40060000
#else #else
#error "Platform not supported"
#endif
#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BS_SIZE 0x00001000
#else /* Default NOR Boot */
#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
#define CONFIG_BS_ADDR_DEVICE 0x60060000 #define CONFIG_BS_ADDR_DEVICE 0x60060000
#define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BS_SIZE 0x00001000 #define CONFIG_BS_SIZE 0x00001000
#endif /* #ifdef CONFIG_SD_BOOT */ #endif
#define CONFIG_BS_HDR_ADDR_RAM 0x81000000 #define CONFIG_BS_HDR_ADDR_RAM 0x81000000
#define CONFIG_BS_ADDR_RAM 0x81020000 #define CONFIG_BS_ADDR_RAM 0x81020000
#endif #endif
@ -109,23 +132,13 @@
#endif #endif
#ifdef CONFIG_FSL_LS_PPA #ifdef CONFIG_FSL_LS_PPA
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
#ifdef CONFIG_LS1043A
#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000
#elif defined(CONFIG_FSL_LSCH3)
#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x580c40000
#endif
#else
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
#endif /* ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP */
/* Define the key hash here if SRK used for signing PPA image is /* Define the key hash here if SRK used for signing PPA image is
* different from SRK hash put in SFP used for U-Boot. * different from SRK hash put in SFP used for U-Boot.
* Example * Example
* #define CONFIG_PPA_KEY_HASH \ * #define PPA_KEY_HASH \
* "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
*/ */
#define CONFIG_PPA_KEY_HASH NULL #define PPA_KEY_HASH NULL
#endif /* ifdef CONFIG_FSL_LS_PPA */ #endif /* ifdef CONFIG_FSL_LS_PPA */
#include <config_fsl_chain_trust.h> #include <config_fsl_chain_trust.h>

6
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -1145,8 +1145,9 @@ switch_as:
li r0,0 li r0,0
1: 1:
dcbz r0,r3 dcbz r0,r3
#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */ #ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */
dcbtls 2, r0, r3 dcbtls 2, r0, r3
dcbtls 0, r0, r3
#else #else
dcbtls 0, r0, r3 dcbtls 0, r0, r3
#endif #endif
@ -1790,8 +1791,9 @@ unlock_ram_in_cache:
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4 mtctr r4
1: dcbi r0,r3 1: dcbi r0,r3
#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */ #ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */
dcblc 2, r0, r3 dcblc 2, r0, r3
dcblc 0, r0, r3
#else #else
dcblc r0,r3 dcblc r0,r3
#endif #endif

2
arch/powerpc/include/asm/fsl_secure_boot.h
View File

@ -100,11 +100,11 @@
#endif /* ifdef CONFIG_SPL_BUILD */ #endif /* ifdef CONFIG_SPL_BUILD */
#define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_ESBC_VALIDATE
#define CONFIG_CMD_BLOB
#define CONFIG_FSL_SEC_MON #define CONFIG_FSL_SEC_MON
#define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_SHA_PROG_HW_ACCEL
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD
#define CONFIG_CMD_BLOB
/* /*
* fsl_setenv_chain_of_trust() must be called from * fsl_setenv_chain_of_trust() must be called from
* board_late_init() * board_late_init()

6
board/freescale/common/arm_sleep.c
View File

@ -13,7 +13,7 @@
#endif #endif
#include <asm/armv7.h> #include <asm/armv7.h>
#if defined(CONFIG_LS102XA) #if defined(CONFIG_ARCH_LS1021A)
#include <asm/arch/immap_ls102xa.h> #include <asm/arch/immap_ls102xa.h>
#endif #endif
@ -66,7 +66,7 @@ static void dp_ddr_restore(void)
*dst++ = *src++; *dst++ = *src++;
} }
#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) #if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
void ls1_psci_resume_fixup(void) void ls1_psci_resume_fixup(void)
{ {
u32 tmp; u32 tmp;
@ -104,7 +104,7 @@ static void dp_resume_prepare(void)
#ifdef CONFIG_U_QE #ifdef CONFIG_U_QE
u_qe_resume(); u_qe_resume();
#endif #endif
#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) #if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
ls1_psci_resume_fixup(); ls1_psci_resume_fixup();
#endif #endif
} }

2
board/freescale/common/fsl_chain_of_trust.c
View File

@ -22,7 +22,7 @@
#include <asm/fsl_pamu.h> #include <asm/fsl_pamu.h>
#endif #endif
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
#include <asm/arch/immap_ls102xa.h> #include <asm/arch/immap_ls102xa.h>
#endif #endif

6
board/freescale/common/fsl_validate.c
View File

@ -15,7 +15,7 @@
#include <u-boot/rsa-mod-exp.h> #include <u-boot/rsa-mod-exp.h>
#include <hash.h> #include <hash.h>
#include <fsl_secboot_err.h> #include <fsl_secboot_err.h>
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
#include <asm/arch/immap_ls102xa.h> #include <asm/arch/immap_ls102xa.h>
#endif #endif
@ -393,6 +393,7 @@ static void fsl_secboot_bootscript_parse_failure(void)
*/ */
void fsl_secboot_handle_error(int error) void fsl_secboot_handle_error(int error)
{ {
#ifndef CONFIG_SPL_BUILD
const struct fsl_secboot_errcode *e; const struct fsl_secboot_errcode *e;
for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX; for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX;
@ -400,6 +401,9 @@ void fsl_secboot_handle_error(int error)
if (e->errcode == error) if (e->errcode == error)
printf("ERROR :: %x :: %s\n", error, e->name); printf("ERROR :: %x :: %s\n", error, e->name);
} }
#else
printf("ERROR :: %x\n", error);
#endif
/* If Boot Mode is secure, transition the SNVS state and issue /* If Boot Mode is secure, transition the SNVS state and issue
* reset based on type of failure and ITS setting. * reset based on type of failure and ITS setting.

4
board/freescale/ls1012ardb/MAINTAINERS
View File

@ -4,3 +4,7 @@ S: Maintained
F: board/freescale/ls1012ardb/ F: board/freescale/ls1012ardb/
F: include/configs/ls1012ardb.h F: include/configs/ls1012ardb.h
F: configs/ls1012ardb_qspi_defconfig F: configs/ls1012ardb_qspi_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig

5
board/freescale/ls1012ardb/ls1012ardb.c
View File

@ -22,6 +22,7 @@
#include <environment.h> #include <environment.h>
#include <fsl_mmdc.h> #include <fsl_mmdc.h>
#include <netdev.h> #include <netdev.h>
#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -118,6 +119,10 @@ int board_init(void)
gd->env_addr = (ulong)&default_environment[0]; gd->env_addr = (ulong)&default_environment[0];
#endif #endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA #ifdef CONFIG_FSL_LS_PPA
ppa_init(); ppa_init();
#endif #endif

2
board/freescale/ls1043aqds/Makefile
View File

@ -5,5 +5,7 @@
# #
obj-y += ddr.o obj-y += ddr.o
ifndef CONFIG_SPL_BUILD
obj-y += eth.o obj-y += eth.o
endif
obj-y += ls1043aqds.o obj-y += ls1043aqds.o

2
board/freescale/ls1043ardb/MAINTAINERS
View File

@ -12,3 +12,5 @@ LS1043A_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com> M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained S: Maintained
F: configs/ls1043ardb_SECURE_BOOT_defconfig F: configs/ls1043ardb_SECURE_BOOT_defconfig
F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig

4
board/freescale/ls1043ardb/Makefile
View File

@ -4,7 +4,9 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# #
obj-y += cpld.o
obj-y += ddr.o obj-y += ddr.o
obj-y += ls1043ardb.o obj-y += ls1043ardb.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
obj-y += cpld.o
endif

18
board/freescale/ls1043ardb/ls1043ardb.c
View File

@ -27,6 +27,15 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return 0;
}
#ifndef CONFIG_SPL_BUILD
int checkboard(void) int checkboard(void)
{ {
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
@ -65,13 +74,6 @@ int checkboard(void)
return 0; return 0;
} }
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return 0;
}
int board_init(void) int board_init(void)
{ {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
@ -213,3 +215,5 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
} }
#endif

4
board/freescale/ls1046aqds/MAINTAINERS
View File

@ -8,3 +8,7 @@ F: configs/ls1046aqds_nand_defconfig
F: configs/ls1046aqds_sdcard_ifc_defconfig F: configs/ls1046aqds_sdcard_ifc_defconfig
F: configs/ls1046aqds_sdcard_qspi_defconfig F: configs/ls1046aqds_sdcard_qspi_defconfig
F: configs/ls1046aqds_qspi_defconfig F: configs/ls1046aqds_qspi_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1046aqds_SECURE_BOOT_defconfig

2
board/freescale/ls1046aqds/Makefile
View File

@ -5,5 +5,7 @@
# #
obj-y += ddr.o obj-y += ddr.o
ifndef CONFIG_SPL_BUILD
obj-y += eth.o obj-y += eth.o
endif
obj-y += ls1046aqds.o obj-y += ls1046aqds.o

19
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -22,6 +22,7 @@
#include <fsl_csu.h> #include <fsl_csu.h>
#include <fsl_esdhc.h> #include <fsl_esdhc.h>
#include <fsl_ifc.h> #include <fsl_ifc.h>
#include <fsl_sec.h>
#include <spl.h> #include <spl.h>
#include "../common/vid.h" #include "../common/vid.h"
@ -266,6 +267,24 @@ int board_init(void)
if (adjust_vdd(0)) if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n"); printf("Warning: Adjusting core voltage failed.\n");
#ifdef CONFIG_SECURE_BOOT
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
* SMMU must be reset in bypass mode.
* Set the ClientPD bit and Clear the USFCFG Bit
*/
u32 val;
val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_SCR0, val);
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0; return 0;
} }

2
board/freescale/ls1046ardb/Kconfig
View File

@ -12,5 +12,5 @@ config SYS_SOC
config SYS_CONFIG_NAME config SYS_CONFIG_NAME
default "ls1046ardb" default "ls1046ardb"
source "board/freescale/common/Kconfig"
endif endif

10
board/freescale/ls1046ardb/MAINTAINERS
View File

@ -7,3 +7,13 @@ F: include/configs/ls1046ardb.h
F: configs/ls1046ardb_qspi_defconfig F: configs/ls1046ardb_qspi_defconfig
F: configs/ls1046ardb_sdcard_defconfig F: configs/ls1046ardb_sdcard_defconfig
F: configs/ls1046ardb_emmc_defconfig F: configs/ls1046ardb_emmc_defconfig
LS1046A_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/ls1046ardb_SECURE_BOOT_defconfig
F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig

4
board/freescale/ls1046ardb/Makefile
View File

@ -4,7 +4,9 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# #
obj-y += cpld.o
obj-y += ddr.o obj-y += ddr.o
obj-y += ls1046ardb.o obj-y += ls1046ardb.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
obj-y += cpld.o
endif

35
board/freescale/ls1046ardb/ls1046ardb.c
View File

@ -21,9 +21,18 @@
#include <fsl_esdhc.h> #include <fsl_esdhc.h>
#include <power/mc34vr500_pmic.h> #include <power/mc34vr500_pmic.h>
#include "cpld.h" #include "cpld.h"
#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return 0;
}
#ifndef CONFIG_SPL_BUILD
int checkboard(void) int checkboard(void)
{ {
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
@ -56,13 +65,6 @@ int checkboard(void)
return 0; return 0;
} }
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return 0;
}
int board_init(void) int board_init(void)
{ {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
@ -71,6 +73,24 @@ int board_init(void)
enable_layerscape_ns_access(); enable_layerscape_ns_access();
#endif #endif
#ifdef CONFIG_SECURE_BOOT
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
* SMMU must be reset in bypass mode.
* Set the ClientPD bit and Clear the USFCFG Bit
*/
u32 val;
val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_SCR0, val);
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA #ifdef CONFIG_FSL_LS_PPA
ppa_init(); ppa_init();
#endif #endif
@ -161,3 +181,4 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0; return 0;
} }
#endif

7
board/freescale/t102xrdb/t102xrdb.c
View File

@ -167,6 +167,13 @@ unsigned long get_board_ddr_clk(void)
return CONFIG_DDR_CLK_FREQ; return CONFIG_DDR_CLK_FREQ;
} }
#ifdef CONFIG_TARGET_T1024RDB
void board_reset(void)
{
CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
}
#endif
int misc_init_r(void) int misc_init_r(void)
{ {
return 0; return 0;

48
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,48 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SECURE_BOOT=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y

1
configs/ls1043ardb_SECURE_BOOT_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y
CONFIG_SECURE_BOOT=y CONFIG_SECURE_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FSL_LS_PPA=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10

57
configs/ls1043ardb_nand_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,57 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y

57
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,57 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y

1
configs/ls1043ardb_sdcard_defconfig
View File

@ -18,7 +18,6 @@ CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y CONFIG_CMD_GPT=y

39
configs/ls1046aqds_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,39 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_RSA=y

1
configs/ls1046aqds_defconfig
View File

@ -36,3 +36,4 @@ CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y CONFIG_FSL_DSPI=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y CONFIG_DM_USB=y
CONFIG_FSL_LS_PPA=y

1
configs/ls1046aqds_lpuart_defconfig
View File

@ -32,3 +32,4 @@ CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y CONFIG_FSL_DSPI=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y CONFIG_DM_USB=y
CONFIG_FSL_LS_PPA=y

1
configs/ls1046aqds_nand_defconfig
View File

@ -41,3 +41,4 @@ CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y CONFIG_FSL_DSPI=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y CONFIG_DM_USB=y
CONFIG_FSL_LS_PPA=y

1
configs/ls1046aqds_qspi_defconfig
View File

@ -38,3 +38,4 @@ CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y CONFIG_FSL_QSPI=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y CONFIG_DM_USB=y
CONFIG_FSL_LS_PPA=y

1
configs/ls1046aqds_sdcard_ifc_defconfig
View File

@ -42,3 +42,4 @@ CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y CONFIG_FSL_DSPI=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y CONFIG_DM_USB=y
CONFIG_FSL_LS_PPA=y

1
configs/ls1046aqds_sdcard_qspi_defconfig
View File

@ -43,3 +43,4 @@ CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y CONFIG_FSL_QSPI=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y CONFIG_DM_USB=y
CONFIG_FSL_LS_PPA=y

37
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,37 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_QSPI_BOOT=y
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_RSA=y

45
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,45 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SECURE_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y

2
configs/ls2080a_emu_defconfig
View File

@ -5,7 +5,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="EMU,LS2080A" CONFIG_SYS_EXTRA_OPTIONS="EMU"
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_CONSOLE is not set

2
configs/ls2080a_simu_defconfig
View File

@ -5,7 +5,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A" CONFIG_SYS_EXTRA_OPTIONS="SIMU"
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_CONSOLE is not set

1
configs/ls2080aqds_SECURE_BOOT_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y CONFIG_CMD_GPT=y

1
configs/ls2080aqds_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y CONFIG_CMD_GPT=y

2
configs/ls2080aqds_nand_defconfig
View File

@ -10,7 +10,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A" CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y

2
configs/ls2080aqds_qspi_defconfig
View File

@ -5,7 +5,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,LS2080A" CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y CONFIG_CMD_GREPENV=y

1
configs/ls2080ardb_SECURE_BOOT_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y CONFIG_CMD_GPT=y

1
configs/ls2080ardb_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y CONFIG_CMD_GPT=y

2
configs/ls2080ardb_nand_defconfig
View File

@ -10,7 +10,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A" CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10 CONFIG_BOOTDELAY=10
CONFIG_SPL=y CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y

4
drivers/crypto/fsl/jobdesc.c
View File

@ -204,7 +204,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc,
append_store(desc, dma_addr_out, storelen, append_store(desc, dma_addr_out, storelen,
LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT); LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT);
} }
#ifndef CONFIG_SPL_BUILD
void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
uint8_t *plain_txt, uint8_t *enc_blob, uint8_t *plain_txt, uint8_t *enc_blob,
uint32_t in_sz) uint32_t in_sz)
@ -252,7 +252,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB); append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB);
} }
#endif
/* /*
* Descriptor to instantiate RNG State Handle 0 in normal mode and * Descriptor to instantiate RNG State Handle 0 in normal mode and
* load the JDKEK, TDKEK and TDSK registers * load the JDKEK, TDKEK and TDSK registers

21
drivers/crypto/fsl/jr.c
View File

@ -341,7 +341,9 @@ static void desc_done(uint32_t status, void *arg)
{ {
struct result *x = arg; struct result *x = arg;
x->status = status; x->status = status;
#ifndef CONFIG_SPL_BUILD
caam_jr_strstatus(status); caam_jr_strstatus(status);
#endif
x->done = 1; x->done = 1;
} }
@ -435,7 +437,11 @@ static inline int sec_reset_idx(uint8_t sec_idx)
return 0; return 0;
} }
int sec_reset(void)
{
return sec_reset_idx(0);
}
#ifndef CONFIG_SPL_BUILD
static int instantiate_rng(uint8_t sec_idx) static int instantiate_rng(uint8_t sec_idx)
{ {
struct result op; struct result op;
@ -471,11 +477,6 @@ static int instantiate_rng(uint8_t sec_idx)
return ret; return ret;
} }
int sec_reset(void)
{
return sec_reset_idx(0);
}
static u8 get_rng_vid(uint8_t sec_idx) static u8 get_rng_vid(uint8_t sec_idx)
{ {
ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
@ -560,7 +561,7 @@ static int rng_init(uint8_t sec_idx)
return ret; return ret;
} }
#endif
int sec_init_idx(uint8_t sec_idx) int sec_init_idx(uint8_t sec_idx)
{ {
ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
@ -585,7 +586,7 @@ int sec_init_idx(uint8_t sec_idx)
* For AXI Read - Cacheable, Read allocate * For AXI Read - Cacheable, Read allocate
* Only For LS2080a, to solve CAAM coherency issues * Only For LS2080a, to solve CAAM coherency issues
*/ */
#ifdef CONFIG_LS2080A #ifdef CONFIG_ARCH_LS2080A
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
#else #else
@ -633,7 +634,7 @@ int sec_init_idx(uint8_t sec_idx)
pamu_enable(); pamu_enable();
#endif #endif
#ifndef CONFIG_SPL_BUILD
if (get_rng_vid(sec_idx) >= 4) { if (get_rng_vid(sec_idx) >= 4) {
if (rng_init(sec_idx) < 0) { if (rng_init(sec_idx) < 0) {
printf("SEC%u: RNG instantiation failed\n", sec_idx); printf("SEC%u: RNG instantiation failed\n", sec_idx);
@ -641,7 +642,7 @@ int sec_init_idx(uint8_t sec_idx)
} }
printf("SEC%u: RNG instantiated\n", sec_idx); printf("SEC%u: RNG instantiated\n", sec_idx);
} }
#endif
return ret; return ret;
} }

72
drivers/ddr/fsl/options.c
View File

@ -33,7 +33,7 @@ struct dynamic_odt {
/* Quad rank is not verified yet due availability. /* Quad rank is not verified yet due availability.
* Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
*/ */
static const struct dynamic_odt single_Q[4] = { static __maybe_unused const struct dynamic_odt single_Q[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS_AND_OTHER_DIMM, FSL_DDR_ODT_CS_AND_OTHER_DIMM,
@ -60,7 +60,7 @@ static const struct dynamic_odt single_Q[4] = {
} }
}; };
static const struct dynamic_odt single_D[4] = { static __maybe_unused const struct dynamic_odt single_D[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -77,7 +77,7 @@ static const struct dynamic_odt single_D[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt single_S[4] = { static __maybe_unused const struct dynamic_odt single_S[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -89,7 +89,7 @@ static const struct dynamic_odt single_S[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
}; };
static const struct dynamic_odt dual_DD[4] = { static __maybe_unused const struct dynamic_odt dual_DD[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_SAME_DIMM, FSL_DDR_ODT_SAME_DIMM,
@ -116,7 +116,7 @@ static const struct dynamic_odt dual_DD[4] = {
} }
}; };
static const struct dynamic_odt dual_DS[4] = { static __maybe_unused const struct dynamic_odt dual_DS[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_SAME_DIMM, FSL_DDR_ODT_SAME_DIMM,
@ -137,7 +137,7 @@ static const struct dynamic_odt dual_DS[4] = {
}, },
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt dual_SD[4] = { static __maybe_unused const struct dynamic_odt dual_SD[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -159,7 +159,7 @@ static const struct dynamic_odt dual_SD[4] = {
} }
}; };
static const struct dynamic_odt dual_SS[4] = { static __maybe_unused const struct dynamic_odt dual_SS[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -176,7 +176,7 @@ static const struct dynamic_odt dual_SS[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt dual_D0[4] = { static __maybe_unused const struct dynamic_odt dual_D0[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_SAME_DIMM, FSL_DDR_ODT_SAME_DIMM,
@ -193,7 +193,7 @@ static const struct dynamic_odt dual_D0[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt dual_0D[4] = { static __maybe_unused const struct dynamic_odt dual_0D[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0},
{ /* cs2 */ { /* cs2 */
@ -210,7 +210,7 @@ static const struct dynamic_odt dual_0D[4] = {
} }
}; };
static const struct dynamic_odt dual_S0[4] = { static __maybe_unused const struct dynamic_odt dual_S0[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS, FSL_DDR_ODT_CS,
@ -223,7 +223,7 @@ static const struct dynamic_odt dual_S0[4] = {
}; };
static const struct dynamic_odt dual_0S[4] = { static __maybe_unused const struct dynamic_odt dual_0S[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0},
{ /* cs2 */ { /* cs2 */
@ -236,7 +236,7 @@ static const struct dynamic_odt dual_0S[4] = {
}; };
static const struct dynamic_odt odt_unknown[4] = { static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS, FSL_DDR_ODT_CS,
@ -263,7 +263,7 @@ static const struct dynamic_odt odt_unknown[4] = {
} }
}; };
#elif defined(CONFIG_SYS_FSL_DDR3) #elif defined(CONFIG_SYS_FSL_DDR3)
static const struct dynamic_odt single_Q[4] = { static __maybe_unused const struct dynamic_odt single_Q[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS_AND_OTHER_DIMM, FSL_DDR_ODT_CS_AND_OTHER_DIMM,
@ -290,7 +290,7 @@ static const struct dynamic_odt single_Q[4] = {
} }
}; };
static const struct dynamic_odt single_D[4] = { static __maybe_unused const struct dynamic_odt single_D[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -307,7 +307,7 @@ static const struct dynamic_odt single_D[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt single_S[4] = { static __maybe_unused const struct dynamic_odt single_S[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -319,7 +319,7 @@ static const struct dynamic_odt single_S[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
}; };
static const struct dynamic_odt dual_DD[4] = { static __maybe_unused const struct dynamic_odt dual_DD[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_SAME_DIMM, FSL_DDR_ODT_SAME_DIMM,
@ -346,7 +346,7 @@ static const struct dynamic_odt dual_DD[4] = {
} }
}; };
static const struct dynamic_odt dual_DS[4] = { static __maybe_unused const struct dynamic_odt dual_DS[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_SAME_DIMM, FSL_DDR_ODT_SAME_DIMM,
@ -367,7 +367,7 @@ static const struct dynamic_odt dual_DS[4] = {
}, },
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt dual_SD[4] = { static __maybe_unused const struct dynamic_odt dual_SD[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -389,7 +389,7 @@ static const struct dynamic_odt dual_SD[4] = {
} }
}; };
static const struct dynamic_odt dual_SS[4] = { static __maybe_unused const struct dynamic_odt dual_SS[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -406,7 +406,7 @@ static const struct dynamic_odt dual_SS[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt dual_D0[4] = { static __maybe_unused const struct dynamic_odt dual_D0[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_SAME_DIMM, FSL_DDR_ODT_SAME_DIMM,
@ -423,7 +423,7 @@ static const struct dynamic_odt dual_D0[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt dual_0D[4] = { static __maybe_unused const struct dynamic_odt dual_0D[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0},
{ /* cs2 */ { /* cs2 */
@ -440,7 +440,7 @@ static const struct dynamic_odt dual_0D[4] = {
} }
}; };
static const struct dynamic_odt dual_S0[4] = { static __maybe_unused const struct dynamic_odt dual_S0[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS, FSL_DDR_ODT_CS,
@ -453,7 +453,7 @@ static const struct dynamic_odt dual_S0[4] = {
}; };
static const struct dynamic_odt dual_0S[4] = { static __maybe_unused const struct dynamic_odt dual_0S[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0},
{ /* cs2 */ { /* cs2 */
@ -466,7 +466,7 @@ static const struct dynamic_odt dual_0S[4] = {
}; };
static const struct dynamic_odt odt_unknown[4] = { static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS, FSL_DDR_ODT_CS,
@ -493,14 +493,14 @@ static const struct dynamic_odt odt_unknown[4] = {
} }
}; };
#else /* CONFIG_SYS_FSL_DDR3 */ #else /* CONFIG_SYS_FSL_DDR3 */
static const struct dynamic_odt single_Q[4] = { static __maybe_unused const struct dynamic_odt single_Q[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt single_D[4] = { static __maybe_unused const struct dynamic_odt single_D[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -517,7 +517,7 @@ static const struct dynamic_odt single_D[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt single_S[4] = { static __maybe_unused const struct dynamic_odt single_S[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -529,7 +529,7 @@ static const struct dynamic_odt single_S[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
}; };
static const struct dynamic_odt dual_DD[4] = { static __maybe_unused const struct dynamic_odt dual_DD[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
@ -556,7 +556,7 @@ static const struct dynamic_odt dual_DD[4] = {
} }
}; };
static const struct dynamic_odt dual_DS[4] = { static __maybe_unused const struct dynamic_odt dual_DS[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
@ -578,7 +578,7 @@ static const struct dynamic_odt dual_DS[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt dual_SD[4] = { static __maybe_unused const struct dynamic_odt dual_SD[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
@ -600,7 +600,7 @@ static const struct dynamic_odt dual_SD[4] = {
} }
}; };
static const struct dynamic_odt dual_SS[4] = { static __maybe_unused const struct dynamic_odt dual_SS[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_OTHER_DIMM,
@ -617,7 +617,7 @@ static const struct dynamic_odt dual_SS[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt dual_D0[4] = { static __maybe_unused const struct dynamic_odt dual_D0[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_ALL, FSL_DDR_ODT_ALL,
@ -634,7 +634,7 @@ static const struct dynamic_odt dual_D0[4] = {
{0, 0, 0, 0} {0, 0, 0, 0}
}; };
static const struct dynamic_odt dual_0D[4] = { static __maybe_unused const struct dynamic_odt dual_0D[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0},
{ /* cs2 */ { /* cs2 */
@ -651,7 +651,7 @@ static const struct dynamic_odt dual_0D[4] = {
} }
}; };
static const struct dynamic_odt dual_S0[4] = { static __maybe_unused const struct dynamic_odt dual_S0[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS, FSL_DDR_ODT_CS,
@ -664,7 +664,7 @@ static const struct dynamic_odt dual_S0[4] = {
}; };
static const struct dynamic_odt dual_0S[4] = { static __maybe_unused const struct dynamic_odt dual_0S[4] = {
{0, 0, 0, 0}, {0, 0, 0, 0},
{0, 0, 0, 0}, {0, 0, 0, 0},
{ /* cs2 */ { /* cs2 */
@ -677,7 +677,7 @@ static const struct dynamic_odt dual_0S[4] = {
}; };
static const struct dynamic_odt odt_unknown[4] = { static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
{ /* cs0 */ { /* cs0 */
FSL_DDR_ODT_NEVER, FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS, FSL_DDR_ODT_CS,

2
drivers/i2c/mxc_i2c.c
View File

@ -589,7 +589,7 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
#endif #endif
static struct mxc_i2c_bus mxc_i2c_buses[] = { static struct mxc_i2c_bus mxc_i2c_buses[] = {
#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \ #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
defined(CONFIG_FSL_LAYERSCAPE) defined(CONFIG_FSL_LAYERSCAPE)
{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },

2
drivers/net/fm/Makefile
View File

@ -34,5 +34,5 @@ obj-$(CONFIG_ARCH_T4240) += t4240.o
obj-$(CONFIG_ARCH_T4160) += t4240.o obj-$(CONFIG_ARCH_T4160) += t4240.o
obj-$(CONFIG_ARCH_B4420) += b4860.o obj-$(CONFIG_ARCH_B4420) += b4860.o
obj-$(CONFIG_ARCH_B4860) += b4860.o obj-$(CONFIG_ARCH_B4860) += b4860.o
obj-$(CONFIG_LS1043A) += ls1043.o obj-$(CONFIG_ARCH_LS1043A) += ls1043.o
obj-$(CONFIG_ARCH_LS1046A) += ls1046.o obj-$(CONFIG_ARCH_LS1046A) += ls1046.o

2
drivers/net/ldpaa_eth/Makefile
View File

@ -6,4 +6,4 @@
obj-y += ldpaa_wriop.o obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o obj-y += ldpaa_eth.o
obj-$(CONFIG_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o

6
drivers/qe/qe.c
View File

@ -13,7 +13,7 @@
#include <asm/io.h> #include <asm/io.h>
#include <linux/immap_qe.h> #include <linux/immap_qe.h>
#include <fsl_qe.h> #include <fsl_qe.h>
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
#include <asm/arch/immap_ls102xa.h> #include <asm/arch/immap_ls102xa.h>
#endif #endif
@ -355,7 +355,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
size_t length; size_t length;
const struct qe_header *hdr; const struct qe_header *hdr;
#ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
#else #else
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@ -494,7 +494,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
size_t length; size_t length;
const struct qe_header *hdr; const struct qe_header *hdr;
#ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
#else #else
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

2
drivers/usb/common/fsl-errata.c
View File

@ -204,7 +204,7 @@ bool has_erratum_a010151(void)
case SVR_LS1043A: case SVR_LS1043A:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif #endif
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
case SOC_VER_LS1020: case SOC_VER_LS1020:
case SOC_VER_LS1021: case SOC_VER_LS1021:
case SOC_VER_LS1022: case SOC_VER_LS1022:

9
include/config_fsl_chain_trust.h
View File

@ -81,17 +81,18 @@
"setenv bs_size " __stringify(CONFIG_BS_SIZE)";" "setenv bs_size " __stringify(CONFIG_BS_SIZE)";"
/* For secure boot flow, default environment used will be used */ /* For secure boot flow, default environment used will be used */
#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_NAND_BOOT) || \
#if defined(CONFIG_RAMBOOT_NAND) defined(CONFIG_SD_BOOT)
#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_NAND_BOOT)
#define CONFIG_BS_COPY_CMD \ #define CONFIG_BS_COPY_CMD \
"nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
"nand read $bs_ram $bs_device $bs_size ;" "nand read $bs_ram $bs_device $bs_size ;"
#endif /* CONFIG_RAMBOOT_NAND */
#elif defined(CONFIG_SD_BOOT) #elif defined(CONFIG_SD_BOOT)
#define CONFIG_BS_COPY_CMD \ #define CONFIG_BS_COPY_CMD \
"mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
"mmc read $bs_ram $bs_device $bs_size ;" "mmc read $bs_ram $bs_device $bs_size ;"
#else /* CONFIG_SD_BOOT */ #endif
#else
#define CONFIG_BS_COPY_CMD \ #define CONFIG_BS_COPY_CMD \
"cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \ "cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \
"cp.b $bs_device $bs_ram $bs_size ;" "cp.b $bs_device $bs_ram $bs_size ;"

2
include/configs/ls1012a_common.h
View File

@ -123,6 +123,4 @@
#define CONFIG_PANIC_HANG #define CONFIG_PANIC_HANG
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#include <asm/fsl_secure_boot.h>
#endif /* __LS1012A_COMMON_H */ #endif /* __LS1012A_COMMON_H */

3
include/configs/ls1012ardb.h
View File

@ -74,4 +74,7 @@
#define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff #define CONFIG_SYS_MEMTEST_END 0x9fffffff
#include <asm/fsl_secure_boot.h>
#endif /* __LS1012ARDB_H__ */ #endif /* __LS1012ARDB_H__ */

2
include/configs/ls1021aiot.h
View File

@ -7,8 +7,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_LS102XA
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_FSL_CLK

2
include/configs/ls1021aqds.h
View File

@ -7,8 +7,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_LS102XA
#define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_PSCI_1_0
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR

2
include/configs/ls1021atwr.h
View File

@ -7,8 +7,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_LS102XA
#define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_PSCI_1_0
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR

72
include/configs/ls1043a_common.h
View File

@ -7,9 +7,27 @@
#ifndef __LS1043A_COMMON_H #ifndef __LS1043A_COMMON_H
#define __LS1043A_COMMON_H #define __LS1043A_COMMON_H
/* SPL build */
#ifdef CONFIG_SPL_BUILD
#define SPL_NO_FMAN
#define SPL_NO_DSPI
#define SPL_NO_PCIE
#define SPL_NO_ENV
#define SPL_NO_MISC
#define SPL_NO_USB
#define SPL_NO_SATA
#define SPL_NO_QE
#define SPL_NO_EEPROM
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
#define SPL_NO_MMC
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
#define SPL_NO_IFC
#endif
#define CONFIG_REMAKE_ELF #define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LAYERSCAPE
#define CONFIG_LS1043A
#define CONFIG_MP #define CONFIG_MP
#define CONFIG_GICV2 #define CONFIG_GICV2
@ -52,7 +70,7 @@
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1d000 #define CONFIG_SPL_MAX_SIZE 0x17000
#define CONFIG_SPL_STACK 0x1001e000 #define CONFIG_SPL_STACK 0x1001e000
#define CONFIG_SPL_PAD_TO 0x1d000 #define CONFIG_SPL_PAD_TO 0x1d000
@ -61,7 +79,19 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_MONITOR_LEN 0xa0000
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
/*
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image. Here u-boot max. size is 512K. So if binary
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_SECURE_BOOT */
#endif #endif
/* NAND SPL */ /* NAND SPL */
@ -79,10 +109,27 @@
#define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_MONITOR_LEN 0xa0000
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */
#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image. Here u-boot max. size is 512K. So if binary
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif #endif
/* IFC */ /* IFC */
#ifndef SPL_NO_IFC
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC #define CONFIG_FSL_IFC
/* /*
@ -103,6 +150,7 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#endif #endif
#endif #endif
#endif
/* I2C */ /* I2C */
#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C
@ -113,6 +161,7 @@
#define CONFIG_SYS_I2C_MXC_I2C4 #define CONFIG_SYS_I2C_MXC_I2C4
/* PCIe */ /* PCIe */
#ifndef SPL_NO_PCIE
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE3 /* PCIE controller 3 */
@ -122,17 +171,23 @@
#define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI #define CONFIG_CMD_PCI
#endif #endif
#endif
/* Command line configuration */ /* Command line configuration */
#ifndef SPL_NO_ENV
#define CONFIG_CMD_ENV #define CONFIG_CMD_ENV
#endif
/* MMC */ /* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC #ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC #define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif #endif
#endif
/* DSPI */ /* DSPI */
#ifndef SPL_NO_DSPI
#define CONFIG_FSL_DSPI #define CONFIG_FSL_DSPI
#ifdef CONFIG_FSL_DSPI #ifdef CONFIG_FSL_DSPI
#define CONFIG_DM_SPI_FLASH #define CONFIG_DM_SPI_FLASH
@ -144,8 +199,10 @@
#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_CS 0
#endif #endif
#endif #endif
#endif
/* FMan ucode */ /* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
@ -177,6 +234,7 @@
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif #endif
#endif
/* Miscellaneous configurable options */ /* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
@ -184,6 +242,7 @@
#define CONFIG_HWCONFIG #define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128 #define HWCONFIG_BUFFER_SIZE 128
#ifndef SPL_NO_MISC
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)" "5m(kernel),1m(dtb),9m(file_system)"
@ -224,6 +283,7 @@
#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
"$kernel_size && bootm $kernel_load" "$kernel_size && bootm $kernel_load"
#endif #endif
#endif
/* Monitor Command Prompt */ /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
@ -231,7 +291,11 @@
sizeof(CONFIG_SYS_PROMPT) + 16) sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_LONGHELP
#ifndef SPL_NO_MISC
#define CONFIG_CMDLINE_EDITING 1 #define CONFIG_CMDLINE_EDITING 1
#endif
#define CONFIG_AUTO_COMPLETE #define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 64 /* max command args */ #define CONFIG_SYS_MAXARGS 64 /* max command args */

16
include/configs/ls1043ardb.h
View File

@ -90,7 +90,9 @@
/* /*
* NAND Flash Definitions * NAND Flash Definitions
*/ */
#ifndef SPL_NO_IFC
#define CONFIG_NAND_FSL_IFC #define CONFIG_NAND_FSL_IFC
#endif
#define CONFIG_SYS_NAND_BASE 0x7e800000 #define CONFIG_SYS_NAND_BASE 0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
@ -134,7 +136,7 @@
#ifdef CONFIG_NAND_BOOT #ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
#endif #endif
/* /*
@ -213,6 +215,7 @@
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
/* EEPROM */ /* EEPROM */
#ifndef SPL_NO_EEPROM
#define CONFIG_ID_EEPROM #define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_EEPROM_BUS_NUM 0
@ -220,11 +223,14 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#endif
/* /*
* Environment * Environment
*/ */
#ifndef SPL_NO_ENV
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
#endif
#if defined(CONFIG_NAND_BOOT) #if defined(CONFIG_NAND_BOOT)
#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_IS_IN_NAND
@ -243,6 +249,7 @@
#endif #endif
/* FMan */ /* FMan */
#ifndef SPL_NO_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET #define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB #define CONFIG_PHYLIB
@ -266,23 +273,29 @@
#define CONFIG_ETHPRIME "FM1@DTSEC3" #define CONFIG_ETHPRIME "FM1@DTSEC3"
#endif #endif
#endif
/* QE */ /* QE */
#ifndef SPL_NO_QE
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT) !defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE #define CONFIG_U_QE
#endif #endif
#define CONFIG_SYS_QE_FW_ADDR 0x60600000 #define CONFIG_SYS_QE_FW_ADDR 0x60600000
#endif
/* USB */ /* USB */
#ifndef SPL_NO_USB
#define CONFIG_HAS_FSL_XHCI_USB #define CONFIG_HAS_FSL_XHCI_USB
#ifdef CONFIG_HAS_FSL_XHCI_USB #ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL #define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif #endif
#endif
/* SATA */ /* SATA */
#ifndef SPL_NO_SATA
#define CONFIG_LIBATA #define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI
#define CONFIG_CMD_SCSI #define CONFIG_CMD_SCSI
@ -299,6 +312,7 @@
#define SCSI_VEND_ID 0x1b4b #define SCSI_VEND_ID 0x1b4b
#define SCSI_DEV_ID 0x9170 #define SCSI_DEV_ID 0x9170
#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
#endif
#include <asm/fsl_secure_boot.h> #include <asm/fsl_secure_boot.h>

48
include/configs/ls1046a_common.h
View File

@ -7,6 +7,23 @@
#ifndef __LS1046A_COMMON_H #ifndef __LS1046A_COMMON_H
#define __LS1046A_COMMON_H #define __LS1046A_COMMON_H
/* SPL build */
#ifdef CONFIG_SPL_BUILD
#define SPL_NO_QBMAN
#define SPL_NO_FMAN
#define SPL_NO_ENV
#define SPL_NO_MISC
#define SPL_NO_QSPI
#define SPL_NO_USB
#define SPL_NO_SATA
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
#define SPL_NO_MMC
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
#define SPL_NO_IFC
#endif
#define CONFIG_REMAKE_ELF #define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LAYERSCAPE
#define CONFIG_MP #define CONFIG_MP
@ -68,7 +85,19 @@
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE) CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SYS_MONITOR_LEN 0xa0000
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
/*
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image. Here u-boot max. size is 512K. So if binary
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_SECURE_BOOT */
#endif #endif
/* NAND SPL */ /* NAND SPL */
@ -88,7 +117,7 @@
#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */ #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
#define CONFIG_SPL_STACK 0x1001f000 #define CONFIG_SPL_STACK 0x1001f000
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
@ -110,20 +139,28 @@
#define CONFIG_SYS_I2C_MXC_I2C4 #define CONFIG_SYS_I2C_MXC_I2C4
/* Command line configuration */ /* Command line configuration */
#ifndef SPL_NO_ENV
#define CONFIG_CMD_ENV #define CONFIG_CMD_ENV
#endif
/* MMC */ /* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC #ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC #define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif #endif
#endif
#ifndef SPL_NO_QBMAN
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#endif
/* FMan ucode */ /* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#endif
#ifdef CONFIG_SD_BOOT #ifdef CONFIG_SD_BOOT
/* /*
@ -157,6 +194,7 @@
#define CONFIG_HWCONFIG #define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128 #define HWCONFIG_BUFFER_SIZE 128
#ifndef SPL_NO_MISC
/* Initial environment variables */ /* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
@ -174,13 +212,19 @@
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500 " \ "earlycon=uart8250,mmio,0x21c0500 " \
MTDPARTS_DEFAULT MTDPARTS_DEFAULT
#endif
/* Monitor Command Prompt */ /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16) sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_LONGHELP
#ifndef SPL_NO_MISC
#define CONFIG_CMDLINE_EDITING 1 #define CONFIG_CMDLINE_EDITING 1
#endif
#define CONFIG_AUTO_COMPLETE #define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 64 /* max command args */ #define CONFIG_SYS_MAXARGS 64 /* max command args */

17
include/configs/ls1046ardb.h
View File

@ -51,13 +51,14 @@
#endif #endif
#endif #endif
#ifndef SPL_NO_IFC
/* IFC */ /* IFC */
#define CONFIG_FSL_IFC #define CONFIG_FSL_IFC
/* /*
* NAND Flash Definitions * NAND Flash Definitions
*/ */
#define CONFIG_NAND_FSL_IFC #define CONFIG_NAND_FSL_IFC
#endif
#define CONFIG_SYS_NAND_BASE 0x7e800000 #define CONFIG_SYS_NAND_BASE 0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
@ -161,7 +162,9 @@
/* /*
* Environment * Environment
*/ */
#ifndef SPL_NO_ENV
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
#endif
#if defined(CONFIG_SD_BOOT) #if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_IS_IN_MMC
@ -176,6 +179,7 @@
#endif #endif
/* FMan */ /* FMan */
#ifndef SPL_NO_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET #define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB #define CONFIG_PHYLIB
@ -196,16 +200,20 @@
#define CONFIG_ETHPRIME "FM1@DTSEC3" #define CONFIG_ETHPRIME "FM1@DTSEC3"
#endif #endif
#endif
/* QSPI device */ /* QSPI device */
#ifndef SPL_NO_QSPI
#ifdef CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_SIZE (1 << 26)
#define FSL_QSPI_FLASH_NUM 2 #define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SPI_FLASH_BAR #define CONFIG_SPI_FLASH_BAR
#endif #endif
#endif
/* USB */ /* USB */
#ifndef SPL_NO_USB
#define CONFIG_HAS_FSL_XHCI_USB #define CONFIG_HAS_FSL_XHCI_USB
#ifdef CONFIG_HAS_FSL_XHCI_USB #ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_HCD #define CONFIG_USB_XHCI_HCD
@ -216,8 +224,10 @@
#define CONFIG_CMD_USB #define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE #define CONFIG_USB_STORAGE
#endif #endif
#endif
/* SATA */ /* SATA */
#ifndef SPL_NO_SATA
#define CONFIG_LIBATA #define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SCSI_AHCI_PLAT
@ -229,7 +239,9 @@
#define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN) CONFIG_SYS_SCSI_MAX_LUN)
#endif
#ifndef SPL_NO_MISC
#define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \ #define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \
"$kernel_start $kernel_size;" \ "$kernel_start $kernel_size;" \
"bootm $kernel_load" "bootm $kernel_load"
@ -238,5 +250,8 @@
"15m(u-boot),48m(kernel.itb);" \ "15m(u-boot),48m(kernel.itb);" \
"7e800000.flash:16m(nand_uboot)," \ "7e800000.flash:16m(nand_uboot)," \
"48m(nand_kernel),448m(nand_free)" "48m(nand_kernel),448m(nand_free)"
#endif
#include <asm/fsl_secure_boot.h>
#endif /* __LS1046ARDB_H__ */ #endif /* __LS1046ARDB_H__ */

4
include/fsl_errata.h
View File

@ -10,7 +10,7 @@
#include <common.h> #include <common.h>
#if defined(CONFIG_PPC) #if defined(CONFIG_PPC)
#include <asm/processor.h> #include <asm/processor.h>
#elif defined(CONFIG_LS102XA) #elif defined(CONFIG_ARCH_LS1021A)
#include <asm/arch-ls102xa/immap_ls102xa.h> #include <asm/arch-ls102xa/immap_ls102xa.h>
#elif defined(CONFIG_FSL_LAYERSCAPE) #elif defined(CONFIG_FSL_LAYERSCAPE)
#include <asm/arch/soc.h> #include <asm/arch/soc.h>
@ -66,7 +66,7 @@ static inline bool has_erratum_a008378(void)
switch (soc) { switch (soc) {
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
case SOC_VER_LS1020: case SOC_VER_LS1020:
case SOC_VER_LS1021: case SOC_VER_LS1021:
case SOC_VER_LS1022: case SOC_VER_LS1022:

2
include/linux/immap_qe.h
View File

@ -24,7 +24,7 @@
#endif #endif
#endif #endif
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
#define QE_MURAM_SIZE 0x6000UL #define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1 #define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28 #define QE_NUM_OF_SNUM 28

6
include/linux/usb/xhci-fsl.h
View File

@ -54,15 +54,15 @@ struct fsl_xhci {
struct dwc3 *dwc3_reg; struct dwc3 *dwc3_reg;
}; };
#if defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A) #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
#elif defined(CONFIG_LS2080A) #elif defined(CONFIG_ARCH_LS2080A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
#elif defined(CONFIG_LS1043A) || defined(CONFIG_ARCH_LS1046A) #elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR

2
include/tsec.h
View File

@ -20,7 +20,7 @@
#ifndef CONFIG_DM_ETH #ifndef CONFIG_DM_ETH
#ifdef CONFIG_LS102XA #ifdef CONFIG_ARCH_LS1021A
#define TSEC_SIZE 0x40000 #define TSEC_SIZE 0x40000
#define TSEC_MDIO_OFFSET 0x40000 #define TSEC_MDIO_OFFSET 0x40000
#else #else

2
include/usb/ehci-ci.h
View File

@ -159,7 +159,7 @@
#elif defined(CONFIG_MPC512X) #elif defined(CONFIG_MPC512X)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
#define CONFIG_SYS_FSL_USB2_ADDR 0 #define CONFIG_SYS_FSL_USB2_ADDR 0
#elif defined(CONFIG_LS102XA) #elif defined(CONFIG_ARCH_LS1021A)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
#define CONFIG_SYS_FSL_USB2_ADDR 0 #define CONFIG_SYS_FSL_USB2_ADDR 0
#endif #endif

3
scripts/config_whitelist.txt
View File

@ -1697,10 +1697,7 @@ CONFIG_LPC_IO_BASE
CONFIG_LPUART CONFIG_LPUART
CONFIG_LPUART_32B_REG CONFIG_LPUART_32B_REG
CONFIG_LQ038J7DH53 CONFIG_LQ038J7DH53
CONFIG_LS102XA
CONFIG_LS102XA_STREAM_ID CONFIG_LS102XA_STREAM_ID
CONFIG_LS1043A
CONFIG_LS2080A
CONFIG_LSCHLV2 CONFIG_LSCHLV2
CONFIG_LSXHL CONFIG_LSXHL
CONFIG_LUAN CONFIG_LUAN