From 424749024a659dec0eef4644375335633b0bf406 Mon Sep 17 00:00:00 2001
From: Ren Jianing <jianing.ren@rock-chips.com>
Date: Tue, 27 Oct 2020 10:05:01 +0800
Subject: [PATCH] rockchip: dts: rk3568: add usb2 phy nodes

Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ib0815580ed2a851598800ac5ef235b313143c00f
---
 arch/arm/dts/rk3568.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
index 52eb87bea0..a462fdf9b1 100644
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -120,6 +120,8 @@
 			reg = <0x0 0xfcc00000 0x0 0x400000>;
 			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 			dr_mode = "otg";
+			phys = <&u2phy0_otg>;
+			phy-names = "usb2-phy";
 			phy_type = "utmi_wide";
 			power-domains = <&power RK3568_PD_PIPE>;
 			resets = <&cru SRST_USB3OTG0>;
@@ -150,6 +152,8 @@
 			reg = <0x0 0xfd000000 0x0 0x400000>;
 			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 			dr_mode = "host";
+			phys = <&u2phy0_host>;
+			phy-names = "usb2-phy";
 			phy_type = "utmi_wide";
 			power-domains = <&power RK3568_PD_PIPE>;
 			resets = <&cru SRST_USB3OTG1>;
@@ -188,6 +192,8 @@
 		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>;
 		clock-names = "usbhost", "arbiter";
+		phys = <&u2phy1_otg>;
+		phy-names = "usb";
 		status = "disabled";
 	};
 
@@ -197,6 +203,8 @@
 		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>;
 		clock-names = "usbhost", "arbiter";
+		phys = <&u2phy1_otg>;
+		phy-names = "usb";
 		status = "disabled";
 	};
 
@@ -206,6 +214,8 @@
 		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>;
 		clock-names = "usbhost", "arbiter";
+		phys = <&u2phy1_host>;
+		phy-names = "usb";
 		status = "disabled";
 	};
 
@@ -215,6 +225,8 @@
 		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>;
 		clock-names = "usbhost", "arbiter";
+		phys = <&u2phy1_host>;
+		phy-names = "usb";
 		status = "disabled";
 	};
 
@@ -258,6 +270,16 @@
 		reg = <0x0 0xfdc90000 0x0 0x1000>;
 	};
 
+	usb2phy0_grf: syscon@fdca0000 {
+		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
+		reg = <0x0 0xfdca0000 0x0 0x8000>;
+	};
+
+	usb2phy1_grf: syscon@fdca8000 {
+		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
+		reg = <0x0 0xfdca8000 0x0 0x8000>;
+	};
+
 	pmucru: clock-controller@fdd00000 {
 		compatible = "rockchip,rk3568-pmucru";
 		reg = <0x0 0xfdd00000 0x0 0x1000>;
@@ -1328,6 +1350,48 @@
 		status = "disabled";
 	};
 
+	usb2phy0: usb2-phy@fe8a0000 {
+		compatible = "rockchip,rk3568-usb2phy";
+		reg = <0x0 0xfe8a0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&pmucru CLK_USBPHY0_REF>;
+		clock-names = "phyclk";
+		#clock-cells = <0>;
+		clock-output-names = "usb480m_phy";
+		rockchip,usbgrf = <&usb2phy0_grf>;
+		status = "disabled";
+
+		u2phy0_host: host-port {
+		#phy-cells = <0>;
+		status = "disabled";
+		};
+
+		u2phy0_otg: otg-port {
+		#phy-cells = <0>;
+		status = "disabled";
+		};
+	};
+
+	usb2phy1: usb2-phy@fe8b0000 {
+		compatible = "rockchip,rk3568-usb2phy";
+		reg = <0x0 0xfe8b0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&pmucru CLK_USBPHY1_REF>;
+		clock-names = "phyclk";
+		rockchip,usbgrf = <&usb2phy1_grf>;
+		status = "disabled";
+
+		u2phy1_host: host-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		u2phy1_otg: otg-port {
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3568-pinctrl";
 		rockchip,grf = <&grf>;