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usb: uniphier: remove UniPhier xHCI driver and select DM_USB 

This driver has not been converted to Driver Model, and it is an
obstacle to migrate other block device drivers.  Remove it for now.

The UniPhier SoCs already use a DM-based EHCI driver, so now
ARCH_UNIPHIER can select DM_USB.

These two changes must be done atomically because removing the
legacy driver causes a build error.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Masahiro Yamada 2016-09-14 01:06:00 +09:00
parent b5550e496e
commit 47a79f657e
8 changed files with 1 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
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@ -861,6 +861,7 @@ config ARCH_UNIPHIER
select DM_I2C select DM_I2C
select DM_MMC select DM_MMC
select DM_SERIAL select DM_SERIAL
select DM_USB
select OF_CONTROL select OF_CONTROL
select OF_LIBFDT select OF_LIBFDT
select SPL select SPL

1
configs/uniphier_ld4_sld8_defconfig
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@ -32,7 +32,6 @@ CONFIG_SPL_NAND_DENALI=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y CONFIG_SPL_PINCTRL=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y

1
configs/uniphier_sld3_defconfig
View File

@ -30,7 +30,6 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y CONFIG_SPL_NAND_DENALI=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y

7
drivers/usb/host/Kconfig
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@ -15,13 +15,6 @@ config USB_XHCI_HCD
if USB_XHCI_HCD if USB_XHCI_HCD
config USB_XHCI_UNIPHIER
bool "Support for UniPhier on-chip xHCI USB controller"
depends on ARCH_UNIPHIER
default y
---help---
Enables support for the on-chip xHCI controller on UniPhier SoCs.
config USB_XHCI_DWC3 config USB_XHCI_DWC3
bool "DesignWare USB3 DRD Core Support" bool "DesignWare USB3 DRD Core Support"
help help

1
drivers/usb/host/Makefile
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@ -62,7 +62,6 @@ obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
# designware # designware
obj-$(CONFIG_USB_DWC2) += dwc2.o obj-$(CONFIG_USB_DWC2) += dwc2.o

85
drivers/usb/host/xhci-uniphier.c
View File

@ -1,85 +0,0 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <usb.h>
#include <fdtdec.h>
#include "xhci.h"
static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
{
DECLARE_GLOBAL_DATA_PTR;
int node_list[2];
fdt_addr_t addr;
int count;
count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
COMPAT_SOCIONEXT_XHCI, node_list,
ARRAY_SIZE(node_list));
if (index >= count)
return -ENODEV;
addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
if (addr == FDT_ADDR_T_NONE)
return -ENODEV;
*base = (struct xhci_hccr *)addr;
return 0;
}
#define USB3_RST_CTRL 0x00100040
#define IOMMU_RST_N (1 << 5)
#define LINK_RST_N (1 << 4)
static void uniphier_xhci_reset(void __iomem *base, int on)
{
u32 tmp;
tmp = readl(base + USB3_RST_CTRL);
if (on)
tmp &= ~(IOMMU_RST_N | LINK_RST_N);
else
tmp |= IOMMU_RST_N | LINK_RST_N;
writel(tmp, base + USB3_RST_CTRL);
}
int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
{
int ret;
struct xhci_hccr *cr;
struct xhci_hcor *or;
ret = get_uniphier_xhci_base(index, &cr);
if (ret < 0)
return ret;
uniphier_xhci_reset(cr, 0);
or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
*hccr = cr;
*hcor = or;
return 0;
}
void xhci_hcd_stop(int index)
{
int ret;
struct xhci_hccr *cr;
ret = get_uniphier_xhci_base(index, &cr);
if (ret < 0)
return;
uniphier_xhci_reset(cr, 1);
}

1
include/fdtdec.h
View File

@ -148,7 +148,6 @@ enum fdt_compat_id {
COMPAT_INTEL_MICROCODE, /* Intel microcode update */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */
COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */
COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */ COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */

1
lib/fdtdec.c
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@ -59,7 +59,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_MICROCODE, "intel,microcode"), COMPAT(INTEL_MICROCODE, "intel,microcode"),
COMPAT(AMS_AS3722, "ams,as3722"), COMPAT(AMS_AS3722, "ams,as3722"),
COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"), COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"), COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"), COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),