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UPSTREAM: arm: arm64 32bit address relocation 

Current relocation code is limited to 21bit PC-relative addressing
which might not be enough for bigger code sizes. The following patch
increases the addressing to 32bit PC-relative. This feature is
specially interesting if U-Boot is build without optimiation (-O0) as
the text section is increased significativelly.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ib54540ff040642588b4bfe2d030e5d9eabf8348c
This commit is contained in:
Ibai Erkiaga 2019-03-15 12:18:41 +00:00 committed by Jianhong Chen
parent 3c3ec66903
commit 559b4bfa7c
1 changed files with 12 additions and 7 deletions
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17
arch/arm/lib/relocate_64.S
View File

@ -27,8 +27,9 @@ ENTRY(relocate_code)
/*
* Copy u-boot from flash to RAM
*/
adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */
subs x9, x0, x1 /* x8 <- Run to copy offset */
adrp x1, __image_copy_start /* x1 <- address bits [31:12] */
add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
subs x9, x0, x1 /* x9 <- Run to copy offset */
b.eq relocate_done /* skip relocation */
/*
* Don't ldr x1, __image_copy_start here, since if the code is already
@ -43,8 +44,10 @@ ENTRY(relocate_code)
ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */
subs x9, x0, x1 /* x9 <- Link to copy offset */
adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */
adr x2, __image_copy_end /* x2 <- Run &__image_copy_end */
adrp x1, __image_copy_start /* x1 <- address bits [31:12] */
add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
adrp x2, __image_copy_end /* x2 <- address bits [31:12] */
add x2, x2, :lo12:__image_copy_end /* x2 <- address bits [11:00] */
copy_loop:
ldp x10, x11, [x1], #16 /* copy from source address [x1] */
stp x10, x11, [x0], #16 /* copy to target address [x0] */
@ -55,8 +58,10 @@ copy_loop:
/*
* Fix .rela.dyn relocations
*/
adr x2, __rel_dyn_start /* x2 <- Run &__rel_dyn_start */
adr x3, __rel_dyn_end /* x3 <- Run &__rel_dyn_end */
adrp x2, __rel_dyn_start /* x2 <- address bits [31:12] */
add x2, x2, :lo12:__rel_dyn_start /* x2 <- address bits [11:00] */
adrp x3, __rel_dyn_end /* x3 <- address bits [31:12] */
add x3, x3, :lo12:__rel_dyn_end /* x3 <- address bits [11:00] */
fixloop:
ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
ldr x4, [x2], #8 /* x4 <- addend */