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pinctrl: rockchip: Add DRV_TYPE_WRITABLE_32BIT and PULL_TYPE_WRITABLE_32BIT for rk3288 gpio0 

Change-Id: Ib17e1b1c3d0aafa437014cc2cb5fb18d13319753
Signed-off-by: David Wu <david.wu@rock-chips.com>
This commit is contained in:
David Wu 2018-04-17 14:21:09 +08:00 committed by Kever Yang
parent a43a18b23b
commit 55a89bc67a
1 changed files with 63 additions and 12 deletions
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63
drivers/pinctrl/pinctrl-rockchip.c
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@ -50,6 +50,9 @@ struct rockchip_iomux {
int offset; int offset;
}; };
#define DRV_TYPE_IO_MASK GENMASK(31, 16)
#define DRV_TYPE_WRITABLE_32BIT BIT(31)
/** /**
* enum type index corresponding to rockchip_perpin_drv_list arrays index. * enum type index corresponding to rockchip_perpin_drv_list arrays index.
*/ */
@ -62,6 +65,9 @@ enum rockchip_pin_drv_type {
DRV_TYPE_MAX DRV_TYPE_MAX
}; };
#define PULL_TYPE_IO_MASK GENMASK(31, 16)
#define PULL_TYPE_WRITABLE_32BIT BIT(31)
/** /**
* enum type index corresponding to rockchip_pull_list arrays index. * enum type index corresponding to rockchip_pull_list arrays index.
*/ */
@ -201,6 +207,32 @@ struct rockchip_pin_bank {
}, \ }, \
} }
#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \
iom2, iom3, drv0, drv1, drv2, \
drv3, pull0, pull1, pull2, \
pull3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = -1 }, \
{ .type = iom1, .offset = -1 }, \
{ .type = iom2, .offset = -1 }, \
{ .type = iom3, .offset = -1 }, \
}, \
.drv = { \
{ .drv_type = drv0, .offset = -1 }, \
{ .drv_type = drv1, .offset = -1 }, \
{ .drv_type = drv2, .offset = -1 }, \
{ .drv_type = drv3, .offset = -1 }, \
}, \
.pull_type[0] = pull0, \
.pull_type[1] = pull1, \
.pull_type[2] = pull2, \
.pull_type[3] = pull3, \
}
#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
label, iom0, iom1, iom2, \ label, iom0, iom1, iom2, \
iom3, drv0, drv1, drv2, \ iom3, drv0, drv1, drv2, \
@ -1665,7 +1697,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
int reg, ret, i; int reg, ret, i;
u32 data, rmask_bits, temp; u32 data, rmask_bits, temp;
u8 bit; u8 bit;
int drv_type = bank->drv[pin_num / 8].drv_type; int drv_type = bank->drv[pin_num / 8].drv_type & DRV_TYPE_IO_MASK;
debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
pin_num, strength); pin_num, strength);
@ -1737,10 +1769,15 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
return -EINVAL; return -EINVAL;
} }
if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) {
regmap_read(regmap, reg, &data);
data &= ~(((1 << rmask_bits) - 1) << bit);
} else {
/* enable the write to the equivalent lower bits */ /* enable the write to the equivalent lower bits */
data = ((1 << rmask_bits) - 1) << (bit + 16); data = ((1 << rmask_bits) - 1) << (bit + 16);
data |= (ret << bit); }
data |= (ret << bit);
ret = regmap_write(regmap, reg, data); ret = regmap_write(regmap, reg, data);
return ret; return ret;
} }
@ -1794,7 +1831,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3308: case RK3308:
case RK3368: case RK3368:
case RK3399: case RK3399:
pull_type = bank->pull_type[pin_num / 8]; pull_type = bank->pull_type[pin_num / 8] & PULL_TYPE_IO_MASK;
ret = -EINVAL; ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
i++) { i++) {
@ -1809,10 +1846,15 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
return ret; return ret;
} }
if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) {
regmap_read(regmap, reg, &data);
data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit);
} else {
/* enable the write to the equivalent lower bits */ /* enable the write to the equivalent lower bits */
data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit); }
data |= (ret << bit);
ret = regmap_write(regmap, reg, data); ret = regmap_write(regmap, reg, data);
break; break;
default: default:
@ -2414,10 +2456,19 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
}; };
static struct rockchip_pin_bank rk3288_pin_banks[] = { static struct rockchip_pin_bank rk3288_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
IOMUX_UNROUTED IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
IOMUX_UNROUTED,
DRV_TYPE_WRITABLE_32BIT,
DRV_TYPE_WRITABLE_32BIT,
DRV_TYPE_WRITABLE_32BIT,
0,
PULL_TYPE_WRITABLE_32BIT,
PULL_TYPE_WRITABLE_32BIT,
PULL_TYPE_WRITABLE_32BIT,
0
), ),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
IOMUX_UNROUTED, IOMUX_UNROUTED,