drivers/reset: support rockchip reset drivers

Create driver to support all Rockchip SoCs soft reset.
Example of usage:
i2c driver:
	ret = reset_get_by_name(dev, "i2c", &reset_ctl);
	if (ret) {
		error("reset_get_by_name() failed: %d\n", ret);
	}

	reset_assert(&reset_ctl);
	udelay(50);
	reset_deassert(&reset_ctl);

i2c dts node:
resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>;
reset-names = "p_i2c", "i2c";

Change-Id: I7db97619e33447d6130e349e90799cd398e29d72
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Elaine Zhang 2017-10-10 15:04:07 +08:00 committed by Kever Yang
parent 39507926d5
commit 5754b8c90d
3 changed files with 113 additions and 0 deletions

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@ -67,4 +67,12 @@ config AST2500_RESET
resets that are supported by watchdog. The main limitation though
is that some reset signals, like I2C or MISC reset multiple devices.
config RESET_ROCKCHIP
bool "Reset controller driver for Rockchip SoCs"
depends on DM_RESET && CLK
default y
help
Support for reset controller on rockchip SoC. The main limitation though
is that some reset signals, like I2C or MISC reset multiple devices.
endmenu

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@ -11,3 +11,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o

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@ -0,0 +1,104 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <reset-uclass.h>
#include <linux/io.h>
struct rockchip_reset_priv {
void __iomem *base;
unsigned int sf_reset_offset;
unsigned int sf_reset_num;
};
static int rockchip_reset_request(struct reset_ctl *reset_ctl)
{
struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (sf_reset_num=%d)\n", __func__,
reset_ctl, reset_ctl->dev, reset_ctl->id, priv->sf_reset_num);
if (reset_ctl->id / 16 >= priv->sf_reset_num)
return -EINVAL;
return 0;
}
static int rockchip_reset_free(struct reset_ctl *reset_ctl)
{
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
reset_ctl->dev, reset_ctl->id);
return 0;
}
static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
{
struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = reset_ctl->id / 16;
int offset = reset_ctl->id % 16;
debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
reset_ctl, reset_ctl->dev, reset_ctl->id,
priv->base + (bank * 4));
writel(BIT(offset) | (BIT(offset) << 16), priv->base + (bank * 4));
return 0;
}
static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
{
struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = reset_ctl->id / 16;
int offset = reset_ctl->id % 16;
debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
reset_ctl, reset_ctl->dev, reset_ctl->id,
priv->base + (bank * 4));
writel((BIT(offset) << 16), priv->base + (bank * 4));
return 0;
}
struct reset_ops rockchip_reset_ops = {
.request = rockchip_reset_request,
.free = rockchip_reset_free,
.rst_assert = rockchip_reset_assert,
.rst_deassert = rockchip_reset_deassert,
};
static int rockchip_reset_probe(struct udevice *dev)
{
struct rockchip_reset_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
fdt_size_t size;
addr = devfdt_get_addr_size_index(dev, 0, &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
if ((priv->sf_reset_offset == 0) && (priv->sf_reset_num == 0))
return -EINVAL;
addr += priv->sf_reset_offset;
priv->base = ioremap(addr, size);
debug("%s(base=%p) (sf_reset_offset=%x, sf_reset_num=%d)\n", __func__,
priv->base, priv->sf_reset_offset, priv->sf_reset_num);
return 0;
}
U_BOOT_DRIVER(rockchip_reset) = {
.name = "rockchip_reset",
.id = UCLASS_RESET,
.probe = rockchip_reset_probe,
.ops = &rockchip_reset_ops,
.priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
};