diff --git a/arch/arm/dts/rockchip-pinconf.dtsi b/arch/arm/dts/rockchip-pinconf.dtsi new file mode 100644 index 0000000000..c13d024019 --- /dev/null +++ b/arch/arm/dts/rockchip-pinconf.dtsi @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ +&pinctrl { + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + drive-strength = <0>; + }; + + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + drive-strength = <1>; + }; + + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + drive-strength = <2>; + }; + + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + drive-strength = <3>; + }; + + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + drive-strength = <4>; + }; + + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + drive-strength = <5>; + }; + + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + drive-strength = <6>; + }; + + pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { + drive-strength = <7>; + }; + + pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { + drive-strength = <8>; + }; + + pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { + drive-strength = <9>; + }; + + pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { + drive-strength = <10>; + }; + + pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { + drive-strength = <11>; + }; + + pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { + drive-strength = <12>; + }; + + pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { + drive-strength = <13>; + }; + + pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { + drive-strength = <14>; + }; + + pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { + drive-strength = <15>; + }; + + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + pcfg_pull_down_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + pcfg_pull_down_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_down_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + pcfg_pull_down_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_pull_down_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + pcfg_pull_down_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + pcfg_pull_down_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + pcfg_pull_down_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_down_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + pcfg_pull_down_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + pcfg_pull_down_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + pcfg_pull_down_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + pcfg_pull_down_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + pcfg_pull_down_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + pcfg_pull_down_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; +}; + diff --git a/arch/arm/dts/rv1109-evb-ddr3-v10.dts b/arch/arm/dts/rv1109-evb-ddr3-v10.dts new file mode 100644 index 0000000000..cc71c36556 --- /dev/null +++ b/arch/arm/dts/rv1109-evb-ddr3-v10.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1109-evb-v10.dtsi" + +/ { + model = "Rockchip RV1109 EVB DDR3 Board"; + compatible = "rockchip,rv1109-evb-ddr3-v10", "rockchip,rv1109"; + + chosen { + bootargs = "clk_ignore_unused earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait"; + }; +}; diff --git a/arch/arm/dts/rv1109-evb-v10.dtsi b/arch/arm/dts/rv1109-evb-v10.dtsi new file mode 100644 index 0000000000..6ffb60883f --- /dev/null +++ b/arch/arm/dts/rv1109-evb-v10.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1109.dtsi" + +/ { + model = "Rockchip RV1109 EVB Board"; + compatible = "rockchip,rv1109-evb-v10", "rockchip,rv1109"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + mmc-hs200-1_8v; + rockchip,default-sample-phase = <90>; + supports-emmc; + status = "okay"; +}; + +&fiq_debugger { + status = "okay"; +}; + +&gmac { + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + assigned-clocks = <&cru CLK_GMAC_SRC>; + assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>; + assigned-clocks = <&cru CLK_GMAC_ETHERNET_OUT>; + assigned-clock-rates = <25000000>; + tx_delay = <0x40>; + rx_delay = <0x3a>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + supports-sdio; + status = "okay"; +}; diff --git a/arch/arm/dts/rv1109.dtsi b/arch/arm/dts/rv1109.dtsi new file mode 100644 index 0000000000..98da788a03 --- /dev/null +++ b/arch/arm/dts/rv1109.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1126.dtsi" + +/ { + compatible = "rockchip,rv1109"; + + cpus { + /delete-node/ cpu@f02; + /delete-node/ cpu@f03; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; + diff --git a/arch/arm/dts/rv1126-dram-default-timing.dtsi b/arch/arm/dts/rv1126-dram-default-timing.dtsi new file mode 100644 index 0000000000..019e7f4387 --- /dev/null +++ b/arch/arm/dts/rv1126-dram-default-timing.dtsi @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include + +/ { + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr2_speed_bin = ; + ddr3_speed_bin = ; + ddr4_speed_bin = ; + pd_idle = <0>; + sr_idle = <0>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + + auto_pd_dis_freq = <1066>; + auto_sr_dis_freq = <800>; + ddr2_dll_dis_freq = <300>; + ddr3_dll_dis_freq = <300>; + ddr4_dll_dis_freq = <625>; + phy_dll_dis_freq = <400>; + + ddr2_odt_dis_freq = <100>; + phy_ddr2_odt_dis_freq = <100>; + ddr2_drv = ; + ddr2_odt = ; + phy_ddr2_ca_drv = ; + phy_ddr2_ck_drv = ; + phy_ddr2_dq_drv = ; + phy_ddr2_odt = ; + + ddr3_odt_dis_freq = <400>; + phy_ddr3_odt_dis_freq = <400>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_ck_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + phy_lpddr2_odt_dis_freq = <666>; + lpddr2_drv = ; + phy_lpddr2_ca_drv = ; + phy_lpddr2_ck_drv = ; + phy_lpddr2_dq_drv = ; + phy_lpddr2_odt = ; + + lpddr3_odt_dis_freq = <400>; + phy_lpddr3_odt_dis_freq = <400>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_ck_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <800>; + phy_lpddr4_odt_dis_freq = <800>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + + ddr4_odt_dis_freq = <666>; + phy_ddr4_odt_dis_freq = <666>; + ddr4_drv = ; + ddr4_odt = ; + phy_ddr4_ca_drv = ; + phy_ddr4_ck_drv = ; + phy_ddr4_dq_drv = ; + phy_ddr4_odt = ; + + /* + * CA de-skew, one step is 20ps, range 0-63 + * name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew + */ + a0_a3_a3_cke1-a_de-skew = <7>; + a1_ba1_null_cke0-b_de-skew = <7>; + a2_a9_a9_a4-a_de-skew = <7>; + a3_a15_null_a5-b_de-skew = <7>; + a4_a6_a6_ck-a_de-skew = <7>; + a5_a12_null_odt0-b_de-skew = <7>; + a6_ba2_null_a0-a_de-skew = <7>; + a7_a4_a4_odt0-a_de-skew = <7>; + a8_a1_a1_cke0-a_de-skew = <7>; + a9_a5_a5_a5-a_de-skew = <7>; + a10_a8_a8_clkb-a_de-skew = <7>; + a11_a7_a7_ca2-a_de-skew = <7>; + a12_rasn_null_ca1-a_de-skew = <7>; + a13_a13_null_ca3-a_de-skew = <7>; + a14_a14_null_csb1-b_de-skew = <7>; + a15_a10_null_ca0-b_de-skew = <7>; + a16_a11_null_csb0-b_de-skew = <7>; + a17_null_null_null_de-skew = <7>; + ba0_csb1_csb1_csb0-a_de-skew = <7>; + ba1_wen_null_cke1-b_de-skew = <7>; + bg0_odt1_odt1_csb1-a_de-skew = <7>; + bg1_a2_a2_odt1-a_de-skew = <7>; + cke0_casb_null_ca1-b_de-skew = <7>; + ck_ck_ck_ck-b_de-skew = <7>; + ckb_ckb_ckb_ckb-b_de-skew = <7>; + csb0_odt0_odt0_ca2-b_de-skew = <7>; + odt0_csb0_csb0_ca4-b_de-skew = <7>; + resetn_resetn_null-resetn_de-skew = <7>; + actn_cke_cke_ca3-b_de-skew = <7>; + cke1_null_null_null_de-skew = <7>; + csb1_ba0_null_null_de-skew = <7>; + odt1_a0_a0_odt1-b_de-skew = <7>; + + /* DATA de-skew, one step is 20ps, range 0-63 */ + /* cs0_skew_a */ + cs0_dm0_rx_de-skew = <7>; + cs0_dq0_rx_de-skew = <7>; + cs0_dq1_rx_de-skew = <7>; + cs0_dq2_rx_de-skew = <7>; + cs0_dq3_rx_de-skew = <7>; + cs0_dq4_rx_de-skew = <7>; + cs0_dq5_rx_de-skew = <7>; + cs0_dq6_rx_de-skew = <7>; + cs0_dq7_rx_de-skew = <7>; + cs0_dqs0p_rx_de-skew = <14>; + cs0_dqs0n_rx_de-skew = <14>; + cs0_dm1_rx_de-skew = <7>; + cs0_dq8_rx_de-skew = <7>; + cs0_dq9_rx_de-skew = <7>; + cs0_dq10_rx_de-skew = <7>; + cs0_dq11_rx_de-skew = <7>; + cs0_dq12_rx_de-skew = <7>; + cs0_dq13_rx_de-skew = <7>; + cs0_dq14_rx_de-skew = <7>; + cs0_dq15_rx_de-skew = <7>; + cs0_dqs1p_rx_de-skew = <14>; + cs0_dqs1n_rx_de-skew = <14>; + cs0_dm0_tx_de-skew = <7>; + cs0_dq0_tx_de-skew = <7>; + cs0_dq1_tx_de-skew = <7>; + cs0_dq2_tx_de-skew = <7>; + cs0_dq3_tx_de-skew = <7>; + cs0_dq4_tx_de-skew = <7>; + cs0_dq5_tx_de-skew = <7>; + cs0_dq6_tx_de-skew = <7>; + cs0_dq7_tx_de-skew = <7>; + cs0_dqs0p_tx_de-skew = <7>; + cs0_dqs0n_tx_de-skew = <7>; + cs0_dm1_tx_de-skew = <7>; + cs0_dq8_tx_de-skew = <7>; + cs0_dq9_tx_de-skew = <7>; + cs0_dq10_tx_de-skew = <7>; + cs0_dq11_tx_de-skew = <7>; + cs0_dq12_tx_de-skew = <7>; + cs0_dq13_tx_de-skew = <7>; + cs0_dq14_tx_de-skew = <7>; + cs0_dq15_tx_de-skew = <7>; + cs0_dqs1p_tx_de-skew = <7>; + cs0_dqs1n_tx_de-skew = <7>; + + /* cs0_skew_b */ + cs0_dm2_rx_de-skew = <7>; + cs0_dq16_rx_de-skew = <7>; + cs0_dq17_rx_de-skew = <7>; + cs0_dq18_rx_de-skew = <7>; + cs0_dq19_rx_de-skew = <7>; + cs0_dq20_rx_de-skew = <7>; + cs0_dq21_rx_de-skew = <7>; + cs0_dq22_rx_de-skew = <7>; + cs0_dq23_rx_de-skew = <7>; + cs0_dqs2p_rx_de-skew = <14>; + cs0_dqs2n_rx_de-skew = <14>; + cs0_dm3_rx_de-skew = <7>; + cs0_dq24_rx_de-skew = <7>; + cs0_dq25_rx_de-skew = <7>; + cs0_dq26_rx_de-skew = <7>; + cs0_dq27_rx_de-skew = <7>; + cs0_dq28_rx_de-skew = <7>; + cs0_dq29_rx_de-skew = <7>; + cs0_dq30_rx_de-skew = <7>; + cs0_dq31_rx_de-skew = <7>; + cs0_dqs3p_rx_de-skew = <14>; + cs0_dqs3n_rx_de-skew = <14>; + cs0_dm2_tx_de-skew = <7>; + cs0_dq16_tx_de-skew = <7>; + cs0_dq17_tx_de-skew = <7>; + cs0_dq18_tx_de-skew = <7>; + cs0_dq19_tx_de-skew = <7>; + cs0_dq20_tx_de-skew = <7>; + cs0_dq21_tx_de-skew = <7>; + cs0_dq22_tx_de-skew = <7>; + cs0_dq23_tx_de-skew = <7>; + cs0_dqs2p_tx_de-skew = <7>; + cs0_dqs2n_tx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_tx_de-skew = <7>; + cs0_dq25_tx_de-skew = <7>; + cs0_dq26_tx_de-skew = <7>; + cs0_dq27_tx_de-skew = <7>; + cs0_dq28_tx_de-skew = <7>; + cs0_dq29_tx_de-skew = <7>; + cs0_dq30_tx_de-skew = <7>; + cs0_dq31_tx_de-skew = <7>; + cs0_dqs3p_tx_de-skew = <7>; + cs0_dqs3n_tx_de-skew = <7>; + + /* cs1_skew_a */ + cs1_dm0_rx_de-skew = <7>; + cs1_dq0_rx_de-skew = <7>; + cs1_dq1_rx_de-skew = <7>; + cs1_dq2_rx_de-skew = <7>; + cs1_dq3_rx_de-skew = <7>; + cs1_dq4_rx_de-skew = <7>; + cs1_dq5_rx_de-skew = <7>; + cs1_dq6_rx_de-skew = <7>; + cs1_dq7_rx_de-skew = <7>; + cs1_dqs0p_rx_de-skew = <14>; + cs1_dqs0n_rx_de-skew = <14>; + cs1_dm1_rx_de-skew = <7>; + cs1_dq8_rx_de-skew = <7>; + cs1_dq9_rx_de-skew = <7>; + cs1_dq10_rx_de-skew = <7>; + cs1_dq11_rx_de-skew = <7>; + cs1_dq12_rx_de-skew = <7>; + cs1_dq13_rx_de-skew = <7>; + cs1_dq14_rx_de-skew = <7>; + cs1_dq15_rx_de-skew = <7>; + cs1_dqs1p_rx_de-skew = <14>; + cs1_dqs1n_rx_de-skew = <14>; + cs1_dm0_tx_de-skew = <7>; + cs1_dq0_tx_de-skew = <7>; + cs1_dq1_tx_de-skew = <7>; + cs1_dq2_tx_de-skew = <7>; + cs1_dq3_tx_de-skew = <7>; + cs1_dq4_tx_de-skew = <7>; + cs1_dq5_tx_de-skew = <7>; + cs1_dq6_tx_de-skew = <7>; + cs1_dq7_tx_de-skew = <7>; + cs1_dqs0p_tx_de-skew = <7>; + cs1_dqs0n_tx_de-skew = <7>; + cs1_dm1_tx_de-skew = <7>; + cs1_dq8_tx_de-skew = <7>; + cs1_dq9_tx_de-skew = <7>; + cs1_dq10_tx_de-skew = <7>; + cs1_dq11_tx_de-skew = <7>; + cs1_dq12_tx_de-skew = <7>; + cs1_dq13_tx_de-skew = <7>; + cs1_dq14_tx_de-skew = <7>; + cs1_dq15_tx_de-skew = <7>; + cs1_dqs1p_tx_de-skew = <7>; + cs1_dqs1n_tx_de-skew = <7>; + + /* cs1_skew_b */ + cs1_dm2_rx_de-skew = <7>; + cs1_dq16_rx_de-skew = <7>; + cs1_dq17_rx_de-skew = <7>; + cs1_dq18_rx_de-skew = <7>; + cs1_dq19_rx_de-skew = <7>; + cs1_dq20_rx_de-skew = <7>; + cs1_dq21_rx_de-skew = <7>; + cs1_dq22_rx_de-skew = <7>; + cs1_dq23_rx_de-skew = <7>; + cs1_dqs2p_rx_de-skew = <14>; + cs1_dqs2n_rx_de-skew = <14>; + cs1_dm3_rx_de-skew = <7>; + cs1_dq24_rx_de-skew = <7>; + cs1_dq25_rx_de-skew = <7>; + cs1_dq26_rx_de-skew = <7>; + cs1_dq27_rx_de-skew = <7>; + cs1_dq28_rx_de-skew = <7>; + cs1_dq29_rx_de-skew = <7>; + cs1_dq30_rx_de-skew = <7>; + cs1_dq31_rx_de-skew = <7>; + cs1_dqs3p_rx_de-skew = <14>; + cs1_dqs3n_rx_de-skew = <14>; + cs1_dm2_tx_de-skew = <7>; + cs1_dq16_tx_de-skew = <7>; + cs1_dq17_tx_de-skew = <7>; + cs1_dq18_tx_de-skew = <7>; + cs1_dq19_tx_de-skew = <7>; + cs1_dq20_tx_de-skew = <7>; + cs1_dq21_tx_de-skew = <7>; + cs1_dq22_tx_de-skew = <7>; + cs1_dq23_tx_de-skew = <7>; + cs1_dqs2p_tx_de-skew = <7>; + cs1_dqs2n_tx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_tx_de-skew = <7>; + cs1_dq25_tx_de-skew = <7>; + cs1_dq26_tx_de-skew = <7>; + cs1_dq27_tx_de-skew = <7>; + cs1_dq28_tx_de-skew = <7>; + cs1_dq29_tx_de-skew = <7>; + cs1_dq30_tx_de-skew = <7>; + cs1_dq31_tx_de-skew = <7>; + cs1_dqs3p_tx_de-skew = <7>; + cs1_dqs3n_tx_de-skew = <7>; + }; +}; diff --git a/arch/arm/dts/rv1126-evb.dts b/arch/arm/dts/rv1126-evb.dts index 7e17cbb986..70a72e5200 100644 --- a/arch/arm/dts/rv1126-evb.dts +++ b/arch/arm/dts/rv1126-evb.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd. */ /dts-v1/; @@ -10,6 +10,12 @@ / { model = "Rockchip RV1126 Evaluation Board"; compatible = "rockchip,rv1126-evb", "rockchip,rv1126"; + + ramdisk-ro { + u-boot,dm-pre-reloc; + compatible = "ramdisk-ro"; + status = "okay"; + }; }; &uart2 { diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi new file mode 100644 index 0000000000..358a33e85d --- /dev/null +++ b/arch/arm/dts/rv1126-pinctrl.dtsi @@ -0,0 +1,1363 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include "rockchip-pinconf.dtsi" + +&pinctrl { + a7 { + a7m0_pins: a7m0-pins { + rockchip,pins = + /* a7_jtag_tck_m0 */ + <1 RK_PA6 3 &pcfg_pull_none>, + /* a7_jtag_tms_m0 */ + <1 RK_PA7 3 &pcfg_pull_none>; + }; + a7m1_pins: a7m1-pins { + rockchip,pins = + /* a7_jtag_tck_m1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* a7_jtag_tms_m1 */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + acodec { + acodec_pins: acodec-pins { + rockchip,pins = + /* acodec_adc_clk */ + <3 RK_PD1 4 &pcfg_pull_none>, + /* acodec_adc_data */ + <3 RK_PD7 3 &pcfg_pull_none>, + /* acodec_adc_sync */ + <3 RK_PD4 3 &pcfg_pull_none>, + /* acodec_dac_clk */ + <3 RK_PD0 3 &pcfg_pull_none>, + /* acodec_dac_datal */ + <3 RK_PD6 3 &pcfg_pull_none>, + /* acodec_dac_datar */ + <3 RK_PD5 3 &pcfg_pull_none>, + /* acodec_dac_sync */ + <3 RK_PD3 3 &pcfg_pull_none>; + }; + }; + auddsm { + auddsm_pins: auddsm-pins { + rockchip,pins = + /* auddsm_ln */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* auddsm_lp */ + <3 RK_PD5 5 &pcfg_pull_none>, + /* auddsm_rn */ + <4 RK_PA0 5 &pcfg_pull_none>, + /* auddsm_rp */ + <4 RK_PA1 5 &pcfg_pull_none>; + }; + }; + audpwm { + audpwmm0_pins: audpwmm0-pins { + rockchip,pins = + /* audpwm_l_m0 */ + <4 RK_PA0 3 &pcfg_pull_none>, + /* audpwm_r_m0 */ + <4 RK_PA1 3 &pcfg_pull_none>; + }; + audpwmm1_pins: audpwmm1-pins { + rockchip,pins = + /* audpwm_l_m1 */ + <3 RK_PD3 4 &pcfg_pull_none>, + /* audpwm_r_m1 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + can { + canm0_pins: canm0-pins { + rockchip,pins = + /* can_rxd_m0 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* can_txd_m0 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + canm1_pins: canm1-pins { + rockchip,pins = + /* can_rxd_m1 */ + <3 RK_PA6 5 &pcfg_pull_none>, + /* can_txd_m1 */ + <3 RK_PA7 5 &pcfg_pull_none>; + }; + }; + cif { + cifm0_dvp_ctl: cifm0-dvp_ctl { + rockchip,pins = + /* cif_clkin_m0 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* cif_clkout_m0 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d0_m0 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* cif_d10_m0 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* cif_d11_m0 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* cif_d12_m0 */ + <3 RK_PC0 1 &pcfg_pull_none>, + /* cif_d13_m0 */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* cif_d14_m0 */ + <3 RK_PC2 1 &pcfg_pull_none>, + /* cif_d15_m0 */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* cif_d1_m0 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* cif_d2_m0 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* cif_d3_m0 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* cif_d4_m0 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* cif_d5_m0 */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* cif_d6_m0 */ + <3 RK_PB2 1 &pcfg_pull_none>, + /* cif_d7_m0 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* cif_d8_m0 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* cif_d9_m0 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* cif_hsync_m0 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_vsync_m0 */ + <3 RK_PC4 1 &pcfg_pull_none>; + }; + cifm1_dvp_ctl: cifm1-dvp_ctl { + rockchip,pins = + /* cif_clkin_m1 */ + <2 RK_PD2 3 &pcfg_pull_none>, + /* cif_clkout_m1 */ + <2 RK_PD1 3 &pcfg_pull_none>, + /* cif_d0_m1 */ + <2 RK_PA4 3 &pcfg_pull_none>, + /* cif_d10_m1 */ + <2 RK_PC2 3 &pcfg_pull_none>, + /* cif_d11_m1 */ + <2 RK_PC3 3 &pcfg_pull_none>, + /* cif_d12_m1 */ + <2 RK_PC4 3 &pcfg_pull_none>, + /* cif_d13_m1 */ + <2 RK_PC5 3 &pcfg_pull_none>, + /* cif_d14_m1 */ + <2 RK_PC6 3 &pcfg_pull_none>, + /* cif_d15_m1 */ + <2 RK_PC7 3 &pcfg_pull_none>, + /* cif_d1_m1 */ + <2 RK_PA5 3 &pcfg_pull_none>, + /* cif_d2_m1 */ + <2 RK_PA6 3 &pcfg_pull_none>, + /* cif_d3_m1 */ + <2 RK_PB3 3 &pcfg_pull_none>, + /* cif_d4_m1 */ + <2 RK_PB4 3 &pcfg_pull_none>, + /* cif_d5_m1 */ + <2 RK_PB5 3 &pcfg_pull_none>, + /* cif_d6_m1 */ + <2 RK_PB6 3 &pcfg_pull_none>, + /* cif_d7_m1 */ + <2 RK_PB7 3 &pcfg_pull_none>, + /* cif_d8_m1 */ + <2 RK_PC0 3 &pcfg_pull_none>, + /* cif_d9_m1 */ + <2 RK_PC1 3 &pcfg_pull_none>, + /* cif_hsync_m1 */ + <2 RK_PD3 3 &pcfg_pull_none>, + /* cif_vsync_m1 */ + <2 RK_PD0 3 &pcfg_pull_none>; + }; + }; + clk { + clkm0_pins: clkm0-pins { + rockchip,pins = + /* clk_out_ethernet_m0 */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + clkm1_pins: clkm1-pins { + rockchip,pins = + /* clk_out_ethernet_m1 */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + clk_32k: clk-32k { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + clk_ref: clk-ref { + rockchip,pins = + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + emmc { + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + flash { + flash_pins: flash-pins { + rockchip,pins = + /* flash_ale */ + <1 RK_PA0 1 &pcfg_pull_none>, + /* flash_cle */ + <0 RK_PD7 1 &pcfg_pull_none>, + /* flash_cs0n */ + <0 RK_PD4 1 &pcfg_pull_none>, + /* flash_d0 */ + <0 RK_PC4 1 &pcfg_pull_none>, + /* flash_d1 */ + <0 RK_PC5 1 &pcfg_pull_none>, + /* flash_d2 */ + <0 RK_PC6 1 &pcfg_pull_none>, + /* flash_d3 */ + <0 RK_PC7 1 &pcfg_pull_none>, + /* flash_d4 */ + <0 RK_PD0 1 &pcfg_pull_none>, + /* flash_d5 */ + <0 RK_PD1 1 &pcfg_pull_none>, + /* flash_d6 */ + <0 RK_PD2 1 &pcfg_pull_none>, + /* flash_d7 */ + <0 RK_PD3 1 &pcfg_pull_none>, + /* flash_rdn */ + <1 RK_PA2 1 &pcfg_pull_none>, + /* flash_rdyn */ + <1 RK_PA1 1 &pcfg_pull_none>, + /* flash_trig_in */ + <1 RK_PC5 4 &pcfg_pull_none>, + /* flash_trig_out */ + <1 RK_PC4 4 &pcfg_pull_none>, + /* flash_vol_sel */ + <0 RK_PB3 1 &pcfg_pull_none>, + /* flash_wpn */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* flash_wrn */ + <0 RK_PD5 1 &pcfg_pull_none>; + }; + }; + fspi { + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PA3 3 &pcfg_pull_none>, + /* fspi_cs0n */ + <0 RK_PD4 3 &pcfg_pull_none>, + /* fspi_cs1n */ + <0 RK_PD1 3 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PA1 3 &pcfg_pull_none>, + /* fspi_d2 */ + <0 RK_PD6 3 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PA2 3 &pcfg_pull_none>; + }; + }; + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB4 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB5 1 &pcfg_pull_none_smt>; + }; + }; + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_scl */ + <1 RK_PD3 1 &pcfg_pull_none_smt>, + /* i2c1_sda */ + <1 RK_PD2 1 &pcfg_pull_none_smt>; + }; + }; + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + /* i2c2_scl */ + <0 RK_PC2 1 &pcfg_pull_none_smt>, + /* i2c2_sda */ + <0 RK_PC3 1 &pcfg_pull_none_smt>; + }; + }; + i2c3 { + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <3 RK_PA4 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <3 RK_PA5 5 &pcfg_pull_none_smt>; + }; + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <2 RK_PD4 7 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <2 RK_PD5 7 &pcfg_pull_none_smt>; + }; + i2c3m2_xfer: i2c3m2-xfer { + rockchip,pins = + /* i2c3_scl_m2 */ + <1 RK_PD6 3 &pcfg_pull_none_smt>, + /* i2c3_sda_m2 */ + <1 RK_PD7 3 &pcfg_pull_none_smt>; + }; + }; + i2c4 { + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <3 RK_PA0 7 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PA1 7 &pcfg_pull_none_smt>; + }; + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <4 RK_PA0 4 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <4 RK_PA1 4 &pcfg_pull_none_smt>; + }; + }; + i2c5 { + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <2 RK_PA5 7 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <2 RK_PB3 7 &pcfg_pull_none_smt>; + }; + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <3 RK_PB0 5 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <3 RK_PB1 5 &pcfg_pull_none_smt>; + }; + i2c5m2_xfer: i2c5m2-xfer { + rockchip,pins = + /* i2c5_scl_m2 */ + <1 RK_PD0 4 &pcfg_pull_none_smt>, + /* i2c5_sda_m2 */ + <1 RK_PD1 4 &pcfg_pull_none_smt>; + }; + }; + i2s0 { + i2s0m0_lrck_rx: i2s0m0-lrck-rx { + rockchip,pins = + <3 RK_PD4 1 &pcfg_pull_none>; + }; + i2s0m0_lrck_tx: i2s0m0-lrck-tx { + rockchip,pins = + <3 RK_PD3 1 &pcfg_pull_none>; + }; + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins = + <3 RK_PD2 1 &pcfg_pull_none>; + }; + i2s0m0_sclk_rx: i2s0m0-sclk-rx { + rockchip,pins = + <3 RK_PD1 1 &pcfg_pull_none>; + }; + i2s0m0_sclk_tx: i2s0m0-sclk-tx { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none>; + }; + i2s0m0_sdi0: i2s0m0-sdi0 { + rockchip,pins = + <3 RK_PD6 1 &pcfg_pull_none>; + }; + i2s0m0_sdo0: i2s0m0-sdo0 { + rockchip,pins = + <3 RK_PD5 1 &pcfg_pull_none>; + }; + i2s0m0_sdo1_sdi3: i2s0m0-sdo1-sdi3 { + rockchip,pins = + <3 RK_PD7 1 &pcfg_pull_none>; + }; + i2s0m0_sdo2_sdi2: i2s0m0-sdo2-sdi2 { + rockchip,pins = + <4 RK_PA0 1 &pcfg_pull_none>; + }; + i2s0m0_sdo3_sdi1: i2s0m0-sdo3-sdi1 { + rockchip,pins = + <4 RK_PA1 1 &pcfg_pull_none>; + }; + i2s0m1_lrck_rx: i2s0m1-lrck-rx { + rockchip,pins = + <3 RK_PB2 3 &pcfg_pull_none>; + }; + i2s0m1_lrck_tx: i2s0m1-lrck-tx { + rockchip,pins = + <3 RK_PA5 3 &pcfg_pull_none>; + }; + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins = + <3 RK_PB0 3 &pcfg_pull_none>; + }; + i2s0m1_sclk_rx: i2s0m1-sclk-rx { + rockchip,pins = + <3 RK_PB1 3 &pcfg_pull_none>; + }; + i2s0m1_sclk_tx: i2s0m1-sclk-tx { + rockchip,pins = + <3 RK_PA4 3 &pcfg_pull_none>; + }; + i2s0m1_sdi0: i2s0m1-sdi0 { + rockchip,pins = + <3 RK_PA7 3 &pcfg_pull_none>; + }; + i2s0m1_sdo0: i2s0m1-sdo0 { + rockchip,pins = + <3 RK_PA6 3 &pcfg_pull_none>; + }; + i2s0m1_sdo1_sdi3: i2s0m1-sdo1-sdi3 { + rockchip,pins = + <3 RK_PB3 3 &pcfg_pull_none>; + }; + i2s0m1_sdo2_sdi2: i2s0m1-sdo2-sdi2 { + rockchip,pins = + <3 RK_PB4 3 &pcfg_pull_none>; + }; + i2s0m1_sdo3_sdi1: i2s0m1-sdo3-sdi1 { + rockchip,pins = + <3 RK_PB5 3 &pcfg_pull_none>; + }; + }; + i2s1 { + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins = + <1 RK_PA0 4 &pcfg_pull_none>; + }; + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + <0 RK_PD4 4 &pcfg_pull_none>; + }; + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins = + <1 RK_PA1 4 &pcfg_pull_none>; + }; + i2s1m0_sdi: i2s1m0-sdi { + rockchip,pins = + <1 RK_PA2 4 &pcfg_pull_none>; + }; + i2s1m0_sdo: i2s1m0-sdo { + rockchip,pins = + <0 RK_PD6 4 &pcfg_pull_none>; + }; + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins = + <1 RK_PD7 2 &pcfg_pull_none>; + }; + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + <1 RK_PD5 2 &pcfg_pull_none>; + }; + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins = + <1 RK_PD6 2 &pcfg_pull_none>; + }; + i2s1m1_sdi: i2s1m1-sdi { + rockchip,pins = + <2 RK_PA0 2 &pcfg_pull_none>; + }; + i2s1m1_sdo: i2s1m1-sdo { + rockchip,pins = + <2 RK_PA1 2 &pcfg_pull_none>; + }; + i2s1m2_lrck: i2s1m2-lrck { + rockchip,pins = + <2 RK_PD2 6 &pcfg_pull_none>; + }; + i2s1m2_mclk: i2s1m2-mclk { + rockchip,pins = + <2 RK_PC7 6 &pcfg_pull_none>; + }; + i2s1m2_sclk: i2s1m2-sclk { + rockchip,pins = + <2 RK_PD1 6 &pcfg_pull_none>; + }; + i2s1m2_sdi: i2s1m2-sdi { + rockchip,pins = + <2 RK_PD3 6 &pcfg_pull_none>; + }; + i2s1m2_sdo: i2s1m2-sdo { + rockchip,pins = + <2 RK_PD0 6 &pcfg_pull_none>; + }; + }; + i2s2 { + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + <1 RK_PC7 1 &pcfg_pull_none>; + }; + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + <1 RK_PD0 1 &pcfg_pull_none>; + }; + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + <1 RK_PC6 1 &pcfg_pull_none>; + }; + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + <1 RK_PC5 1 &pcfg_pull_none>; + }; + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + <1 RK_PC4 1 &pcfg_pull_none>; + }; + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + <2 RK_PB2 2 &pcfg_pull_none>; + }; + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + <2 RK_PB3 2 &pcfg_pull_none>; + }; + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + <2 RK_PB1 2 &pcfg_pull_none>; + }; + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + <2 RK_PB0 2 &pcfg_pull_none>; + }; + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + <2 RK_PA7 2 &pcfg_pull_none>; + }; + }; + lcdc { + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* lcdc_clk */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d0 */ + <2 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d1 */ + <2 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <2 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <2 RK_PC0 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <2 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <2 RK_PC2 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <2 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_d16 */ + <2 RK_PC4 1 &pcfg_pull_none>, + /* lcdc_d17 */ + <2 RK_PC5 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <2 RK_PC6 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <2 RK_PC7 1 &pcfg_pull_none>, + /* lcdc_d2 */ + <2 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <2 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <2 RK_PD1 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PB1 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PB2 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d8 */ + <2 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <2 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_den */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <2 RK_PD6 1 &pcfg_pull_none>; + }; + }; + mcu { + mcu_pins: mcu-pins { + rockchip,pins = + /* mcu_jtag_tck */ + <1 RK_PA6 4 &pcfg_pull_none>, + /* mcu_jtag_tdi */ + <1 RK_PB1 4 &pcfg_pull_none>, + /* mcu_jtag_tdo */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* mcu_jtag_tms */ + <1 RK_PA7 4 &pcfg_pull_none>, + /* mcu_jtag_trstn */ + <1 RK_PA5 4 &pcfg_pull_none>; + }; + }; + mipi { + mipim1_pins: mipim1-pins { + rockchip,pins = + /* mipi_csi_clk1_m1 */ + <2 RK_PA2 1 &pcfg_pull_none>; + }; + mipi_csi_clk0: mipi-csi-clk0 { + rockchip,pins = + <2 RK_PA3 1 &pcfg_pull_none>; + }; + }; + pdm { + pdmm0_clk: pdmm0-clk { + rockchip,pins = + /* pdm_clk0_m0 */ + <3 RK_PD4 2 &pcfg_pull_none>; + }; + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + <3 RK_PD1 2 &pcfg_pull_none>; + }; + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + <3 RK_PD6 2 &pcfg_pull_none>; + }; + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + <4 RK_PA1 2 &pcfg_pull_none>; + }; + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + <4 RK_PA0 2 &pcfg_pull_none>; + }; + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + <3 RK_PD7 2 &pcfg_pull_none>; + }; + pdmm1_clk: pdmm1-clk { + rockchip,pins = + /* pdm_clk0_m1 */ + <3 RK_PC0 3 &pcfg_pull_none>; + }; + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + <3 RK_PC3 3 &pcfg_pull_none>; + }; + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + <3 RK_PC1 3 &pcfg_pull_none>; + }; + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + <3 RK_PC2 3 &pcfg_pull_none>; + }; + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + <3 RK_PB6 3 &pcfg_pull_none>; + }; + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + <3 RK_PB7 3 &pcfg_pull_none>; + }; + }; + pmic { + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_int */ + <0 RK_PB1 1 &pcfg_pull_none>, + /* pmic_sleep */ + <0 RK_PB2 1 &pcfg_pull_none>; + }; + }; + pmu { + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + }; + prelight { + prelight_pins: prelight-pins { + rockchip,pins = + /* prelight_trig_out */ + <1 RK_PC6 4 &pcfg_pull_none>; + }; + }; + pwm0 { + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB6 3 &pcfg_pull_none>; + }; + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <2 RK_PB3 5 &pcfg_pull_none>; + }; + }; + pwm1 { + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <2 RK_PB2 5 &pcfg_pull_none>; + }; + }; + pwm10 { + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PA6 6 &pcfg_pull_none>; + }; + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <2 RK_PD5 5 &pcfg_pull_none>; + }; + }; + pwm11 { + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_ir_m0 */ + <3 RK_PA7 6 &pcfg_pull_none>; + }; + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_ir_m1 */ + <2 RK_PD4 5 &pcfg_pull_none>; + }; + }; + pwm2 { + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <2 RK_PB1 5 &pcfg_pull_none>; + }; + }; + pwm3 { + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_ir_m0 */ + <0 RK_PC1 3 &pcfg_pull_none>; + }; + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_ir_m1 */ + <2 RK_PB0 5 &pcfg_pull_none>; + }; + }; + pwm4 { + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <2 RK_PA7 5 &pcfg_pull_none>; + }; + }; + pwm5 { + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <0 RK_PC3 3 &pcfg_pull_none>; + }; + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <2 RK_PA6 5 &pcfg_pull_none>; + }; + }; + pwm6 { + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <0 RK_PB2 3 &pcfg_pull_none>; + }; + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <3 RK_PA1 5 &pcfg_pull_none>; + }; + }; + pwm7 { + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_ir_m0 */ + <0 RK_PB1 3 &pcfg_pull_none>; + }; + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_ir_m1 */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + }; + pwm8 { + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PA4 6 &pcfg_pull_none>; + }; + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <2 RK_PD7 5 &pcfg_pull_none>; + }; + }; + pwm9 { + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PA5 6 &pcfg_pull_none>; + }; + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <2 RK_PD6 5 &pcfg_pull_none>; + }; + }; + rgmii { + rgmiim0_pins: rgmiim0-pins { + rockchip,pins = + /* rgmii_clk_m0 */ + <3 RK_PC0 2 &pcfg_pull_none>, + /* rgmii_col_m0 */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_crs_m0 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_mdc_m0 */ + <3 RK_PC4 2 &pcfg_pull_none>, + /* rgmii_mdio_m0 */ + <3 RK_PC3 2 &pcfg_pull_none>, + /* rgmii_rxclk_m0 */ + <3 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd0_m0 */ + <3 RK_PB6 2 &pcfg_pull_none>, + /* rgmii_rxd1_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>, + /* rgmii_rxd2_m0 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m0 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* rgmii_rxdv_m0 */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_rxer_m0 */ + <3 RK_PC2 2 &pcfg_pull_none>, + /* rgmii_txclk_m0 */ + <3 RK_PC6 2 &pcfg_pull_none>, + /* rgmii_txd0_m0 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* rgmii_txd1_m0 */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* rgmii_txd2_m0 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* rgmii_txd3_m0 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* rgmii_txen_m0 */ + <3 RK_PB5 2 &pcfg_pull_none>; + }; + rgmiim1_pins: rgmiim1-pins { + rockchip,pins = + /* rgmii_clk_m1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* rgmii_col_m1 */ + <2 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_crs_m1 */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_mdc_m1 */ + <2 RK_PC2 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <2 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_rxclk_m1 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* rgmii_rxd0_m1 */ + <2 RK_PB5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <2 RK_PB6 2 &pcfg_pull_none>, + /* rgmii_rxd2_m1 */ + <2 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <2 RK_PB4 2 &pcfg_pull_none>, + /* rgmii_rxer_m1 */ + <2 RK_PC0 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* rgmii_txd0_m1 */ + <2 RK_PC3 2 &pcfg_pull_none>, + /* rgmii_txd1_m1 */ + <2 RK_PC4 2 &pcfg_pull_none>, + /* rgmii_txd2_m1 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* rgmii_txd3_m1 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* rgmii_txen_m1 */ + <2 RK_PC6 2 &pcfg_pull_none>; + }; + }; + sdmmc0 { + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + sdmmc0_det: sdmmc0-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_none>; + }; + sdmmc0_pwr: sdmmc0-pwr { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + sdmmc1 { + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + sdmmc1_det: sdmmc1-det { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none>; + }; + sdmmc1_pwr: sdmmc1-pwr { + rockchip,pins = + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + spi0 { + spi0m0_clk: spi0m0-clk { + rockchip,pins = + <0 RK_PB0 1 &pcfg_pull_none>; + }; + spi0m0_cs0n: spi0m0-cs0n { + rockchip,pins = + <0 RK_PA5 1 &pcfg_pull_none>; + }; + spi0m0_cs1n: spi0m0-cs1n { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + spi0m0_miso: spi0m0-miso { + rockchip,pins = + <0 RK_PA7 1 &pcfg_pull_none>; + }; + spi0m0_mosi: spi0m0-mosi { + rockchip,pins = + <0 RK_PA6 1 &pcfg_pull_none>; + }; + spi0m1_clk: spi0m1-clk { + rockchip,pins = + <2 RK_PA1 1 &pcfg_pull_none>; + }; + spi0m1_cs0n: spi0m1-cs0n { + rockchip,pins = + <2 RK_PA0 1 &pcfg_pull_none>; + }; + spi0m1_cs1n: spi0m1-cs1n { + rockchip,pins = + <1 RK_PD5 1 &pcfg_pull_none>; + }; + spi0m1_miso: spi0m1-miso { + rockchip,pins = + <1 RK_PD7 1 &pcfg_pull_none>; + }; + spi0m1_mosi: spi0m1-mosi { + rockchip,pins = + <1 RK_PD6 1 &pcfg_pull_none>; + }; + spi0m2_clk: spi0m2-clk { + rockchip,pins = + <2 RK_PB2 6 &pcfg_pull_none>; + }; + spi0m2_cs0n: spi0m2-cs0n { + rockchip,pins = + <2 RK_PA7 6 &pcfg_pull_none>; + }; + spi0m2_cs1n: spi0m2-cs1n { + rockchip,pins = + <2 RK_PB3 6 &pcfg_pull_none>; + }; + spi0m2_miso: spi0m2-miso { + rockchip,pins = + <2 RK_PB1 6 &pcfg_pull_none>; + }; + spi0m2_mosi: spi0m2-mosi { + rockchip,pins = + <2 RK_PB0 6 &pcfg_pull_none>; + }; + }; + spi1 { + spi1m0_clk: spi1m0-clk { + rockchip,pins = + <3 RK_PC0 5 &pcfg_pull_none>; + }; + spi1m0_cs0n: spi1m0-cs0n { + rockchip,pins = + <3 RK_PB5 5 &pcfg_pull_none>; + }; + spi1m0_cs1n: spi1m0-cs1n { + rockchip,pins = + <3 RK_PB4 5 &pcfg_pull_none>; + }; + spi1m0_miso: spi1m0-miso { + rockchip,pins = + <3 RK_PB7 5 &pcfg_pull_none>; + }; + spi1m0_mosi: spi1m0-mosi { + rockchip,pins = + <3 RK_PB6 5 &pcfg_pull_none>; + }; + spi1m1_clk: spi1m1-clk { + rockchip,pins = + <1 RK_PC6 3 &pcfg_pull_none>; + }; + spi1m1_cs0n: spi1m1-cs0n { + rockchip,pins = + <1 RK_PC7 3 &pcfg_pull_none>; + }; + spi1m1_cs1n: spi1m1-cs1n { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_none>; + }; + spi1m1_miso: spi1m1-miso { + rockchip,pins = + <1 RK_PC5 3 &pcfg_pull_none>; + }; + spi1m1_mosi: spi1m1-mosi { + rockchip,pins = + <1 RK_PC4 3 &pcfg_pull_none>; + }; + spi1m2_clk: spi1m2-clk { + rockchip,pins = + <2 RK_PD5 6 &pcfg_pull_none>; + }; + spi1m2_cs0n: spi1m2-cs0n { + rockchip,pins = + <2 RK_PD4 6 &pcfg_pull_none>; + }; + spi1m2_cs1n: spi1m2-cs1n { + rockchip,pins = + <3 RK_PA0 6 &pcfg_pull_none>; + }; + spi1m2_miso: spi1m2-miso { + rockchip,pins = + <2 RK_PD7 6 &pcfg_pull_none>; + }; + spi1m2_mosi: spi1m2-mosi { + rockchip,pins = + <2 RK_PD6 6 &pcfg_pull_none>; + }; + }; + tsadc { + tsadcm0_pins: tsadcm0-pins { + rockchip,pins = + /* tsadc_shut_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + tsadcm1_pins: tsadcm1-pins { + rockchip,pins = + /* tsadc_shut_m1 */ + <0 RK_PB2 2 &pcfg_pull_none>; + }; + tsadc_shutorg: tsadc-shutorg { + rockchip,pins = + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <1 RK_PC2 1 &pcfg_pull_up>, + /* uart0_tx */ + <1 RK_PC3 1 &pcfg_pull_up>; + }; + uart0_ctsn: uart0-ctsn { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_none>; + }; + uart0_rtsn: uart0-rtsn { + rockchip,pins = + <1 RK_PC0 1 &pcfg_pull_none>; + }; + }; + uart1 { + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB6 2 &pcfg_pull_up>; + }; + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + <0 RK_PC1 2 &pcfg_pull_none>; + }; + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + <0 RK_PC0 2 &pcfg_pull_none>; + }; + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <1 RK_PD1 5 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <1 RK_PD0 5 &pcfg_pull_up>; + }; + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + <1 RK_PC7 5 &pcfg_pull_none>; + }; + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + <1 RK_PC6 5 &pcfg_pull_none>; + }; + }; + uart2 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <1 RK_PA4 3 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <1 RK_PA5 3 &pcfg_pull_up>; + }; + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA3 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA2 1 &pcfg_pull_up>; + }; + }; + uart3 { + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <3 RK_PC6 4 &pcfg_pull_up>; + }; + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + <3 RK_PC5 4 &pcfg_pull_none>; + }; + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + <3 RK_PC4 4 &pcfg_pull_none>; + }; + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <1 RK_PA6 2 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <1 RK_PA7 2 &pcfg_pull_up>; + }; + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + /* uart3_rx_m2 */ + <3 RK_PA1 4 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <3 RK_PA0 4 &pcfg_pull_up>; + }; + uart3m2_ctsn: uart3m2-ctsn { + rockchip,pins = + <2 RK_PD7 4 &pcfg_pull_none>; + }; + uart3m2_rtsn: uart3m2-rtsn { + rockchip,pins = + <2 RK_PD6 4 &pcfg_pull_none>; + }; + uart3_ctsn: uart3-ctsn { + rockchip,pins = + <1 RK_PB1 2 &pcfg_pull_none>; + }; + uart3_rtsn: uart3-rtsn { + rockchip,pins = + <1 RK_PB0 2 &pcfg_pull_none>; + }; + }; + uart4 { + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PA5 4 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PA4 4 &pcfg_pull_up>; + }; + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + <3 RK_PB3 4 &pcfg_pull_none>; + }; + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + <3 RK_PB2 4 &pcfg_pull_none>; + }; + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rx_m1 */ + <2 RK_PA7 4 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <2 RK_PA6 4 &pcfg_pull_up>; + }; + uart4m1_ctsn: uart4m1-ctsn { + rockchip,pins = + <2 RK_PA5 4 &pcfg_pull_none>; + }; + uart4m1_rtsn: uart4m1-rtsn { + rockchip,pins = + <2 RK_PA4 4 &pcfg_pull_none>; + }; + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + /* uart4_rx_m2 */ + <1 RK_PD4 3 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; + uart4m2_ctsn: uart4m2-ctsn { + rockchip,pins = + <1 RK_PD3 3 &pcfg_pull_none>; + }; + uart4m2_rtsn: uart4m2-rtsn { + rockchip,pins = + <1 RK_PD2 3 &pcfg_pull_none>; + }; + }; + uart5 { + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + <3 RK_PB1 4 &pcfg_pull_none>; + }; + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + <3 RK_PB0 4 &pcfg_pull_none>; + }; + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <2 RK_PB1 4 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <2 RK_PB0 4 &pcfg_pull_up>; + }; + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + <2 RK_PB3 4 &pcfg_pull_none>; + }; + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + <2 RK_PB2 4 &pcfg_pull_none>; + }; + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PA0 3 &pcfg_pull_up>; + }; + uart5m2_ctsn: uart5m2-ctsn { + rockchip,pins = + <2 RK_PA3 3 &pcfg_pull_none>; + }; + uart5m2_rtsn: uart5m2-rtsn { + rockchip,pins = + <2 RK_PA2 3 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi index 744a860286..7c84239601 100644 --- a/arch/arm/dts/rv1126-u-boot.dtsi +++ b/arch/arm/dts/rv1126-u-boot.dtsi @@ -1,15 +1,45 @@ /* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: GPL-2.0+ */ / { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + chosen { stdout-path = &uart2; }; }; +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&pmu { + u-boot,dm-pre-reloc; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&pmucru { + u-boot,dm-pre-reloc; +}; + &cru { u-boot,dm-pre-reloc; }; @@ -17,8 +47,3 @@ &grf { u-boot,dm-pre-reloc; }; - -&uart2 { - u-boot,dm-pre-reloc; - clock-frequency = <24000000>; -}; diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi index 05ea31c5fd..c420dfe88a 100644 --- a/arch/arm/dts/rv1126.dtsi +++ b/arch/arm/dts/rv1126.dtsi @@ -4,9 +4,13 @@ */ #include +#include #include #include #include +#include +#include +#include "rv1126-dram-default-timing.dtsi" / { #address-cells = <1>; @@ -17,6 +21,12 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -34,24 +44,58 @@ compatible = "arm,cortex-a7"; reg = <0xf00>; clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@f01 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf01>; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@f02 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf02>; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@f03 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf03>; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000 800000 945000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000 800000 945000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <800000 800000 945000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <800000 800000 945000>; + clock-latency-ns = <40000>; }; }; @@ -64,6 +108,44 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <0>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + status = "disabled"; + }; + + rgb: rgb { + compatible = "rockchip,rv1126-rgb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_rgb>; + }; + }; + + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -85,6 +167,116 @@ reg = <0xfe000000 0x1000>; }; + pmugrf: syscon@fe020000 { + compatible = "rockchip,rv1126-pmugrf", "syscon"; + reg = <0xfe020000 0x1000>; + }; + + qos_usb_host: qos@fe810008 { + compatible = "syscon"; + reg = <0xfe810008 0x20>; + }; + + qos_usb_otg: qos@fe810088 { + compatible = "syscon"; + reg = <0xfe810088 0x20>; + }; + + qos_npu: qos@fe850008 { + compatible = "syscon"; + reg = <0xfe850008 0x20>; + }; + + qos_emmc: qos@fe860008 { + compatible = "syscon"; + reg = <0xfe860008 0x20>; + }; + + qos_nandc: qos@fe860088 { + compatible = "syscon"; + reg = <0xe860088 0x20>; + }; + + qos_sfc: qos@fe860208 { + compatible = "syscon"; + reg = <0xfe860208 0x20>; + }; + + qos_sdmmc: qos@fe868008 { + compatible = "syscon"; + reg = <0xfe868008 0x20>; + }; + + qos_sdio: qos@fe86c008 { + compatible = "syscon"; + reg = <0xfe86c008 0x20>; + }; + + qos_vepu_rd0: qos@fe870008 { + compatible = "syscon"; + reg = <0xfe870008 0x20>; + }; + + qos_vepu_rd1: qos@fe870088 { + compatible = "syscon"; + reg = <0xfe870088 0x20>; + }; + + qos_vepu_wr: qos@fe870108 { + compatible = "syscon"; + reg = <0xfe870108 0x20>; + }; + + qos_ispp_m0: qos@fe880018 { + compatible = "syscon"; + reg = <0xfe880018 0x20>; + }; + + qos_ispp_m1: qos@fe880098 { + compatible = "syscon"; + reg = <0xfe880098 0x20>; + }; + + qos_isp: qos@fe890008 { + compatible = "syscon"; + reg = <0xfe890008 0x20>; + }; + + qos_cif_lite: qos@fe890088 { + compatible = "syscon"; + reg = <0xfe890088 0x20>; + }; + + qos_cif: qos@fe890108 { + compatible = "syscon"; + reg = <0xfe890108 0x20>; + }; + + qos_iep: qos@fe8a0008 { + compatible = "syscon"; + reg = <0xfe8a0008 0x20>; + }; + + qos_rga_rd: qos@fe8a0088 { + compatible = "syscon"; + reg = <0xfe8a0088 0x20>; + }; + + qos_rga_wr: qos@fe8a0108 { + compatible = "syscon"; + reg = <0xfe8a0108 0x20>; + }; + + qos_vop: qos@fe8a0188 { + compatible = "syscon"; + reg = <0xfe8a0188 0x20>; + }; + + qos_vdpu: qos@fe8b0008 { + compatible = "syscon"; + reg = <0xfe8b0008 0x20>; + }; + gic: interrupt-controller@feff0000 { compatible = "arm,gic-400"; interrupt-controller; @@ -98,6 +290,157 @@ interrupts = ; }; + pvtm@ff040000 { + compatible = "rockchip,rv1126-cpu-pvtm"; + reg = <0xff040000 0x100>; + clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>; + reset-names = "clk", "pclk"; + }; + + pmu: power-management@ff3e0000 { + compatible = "rockchip,rv1126-pmu", "syscon"; + reg = <0xff3e0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rv1126-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* These power domains are grouped by VD_NPU */ + pd_npu@RV1126_PD_NPU { + reg = ; + clocks = <&cru ACLK_NPU>, + <&cru HCLK_NPU>, + <&cru PCLK_PDNPU>, + <&cru CLK_CORE_NPU>; + pm_qos = <&qos_npu>; + }; + /* These power domains are grouped by VD_VEPU */ + pd_vepu@RV1126_PD_VEPU { + reg = ; + clocks = <&cru ACLK_VENC>, + <&cru HCLK_VENC>, + <&cru CLK_VENC_CORE>; + pm_qos = <&qos_vepu_rd0>, + <&qos_vepu_rd1>, + <&qos_vepu_wr>; + }; + /* These power domains are grouped by VD_LOGIC */ + pd_vi@RV1126_PD_VI { + reg = ; + clocks = <&cru ACLK_ISP>, + <&cru HCLK_ISP>, + <&cru CLK_ISP>, + <&cru ACLK_CIF>, + <&cru HCLK_CIF>, + <&cru DCLK_CIF>, + <&cru CLK_CIF_OUT>, + <&cru CLK_MIPICSI_OUT>, + <&cru PCLK_CSIHOST>, + <&cru ACLK_CIFLITE>, + <&cru HCLK_CIFLITE>, + <&cru DCLK_CIFLITE>; + pm_qos = <&qos_isp>, + <&qos_cif_lite>, + <&qos_cif>; + }; + pd_vo@RV1126_PD_VO { + reg = ; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru CLK_RGA_CORE>, + <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP>, + <&cru PCLK_DSIHOST>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru CLK_IEP_CORE>; + pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, + <&qos_vop>, <&qos_iep>; + }; + pd_ispp@RV1126_PD_ISPP { + reg = ; + clocks = <&cru ACLK_ISPP>, + <&cru HCLK_ISPP>, + <&cru CLK_ISPP>; + pm_qos = <&qos_ispp_m0>, + <&qos_ispp_m1>; + }; + pd_vdpu@RV1126_PD_VDPU { + reg = ; + clocks = <&cru ACLK_VDEC>, + <&cru HCLK_VDEC>, + <&cru CLK_VDEC_CORE>, + <&cru CLK_VDEC_CA>, + <&cru CLK_VDEC_HEVC_CA>, + <&cru ACLK_JPEG>, + <&cru HCLK_JPEG>; + pm_qos = <&qos_vdpu>; + }; + pd_nvm@RV1126_PD_NVM { + reg = ; + clocks = <&cru HCLK_EMMC>, + <&cru CLK_EMMC>, + <&cru HCLK_NANDC>, + <&cru CLK_NANDC>, + <&cru HCLK_SFC>, + <&cru HCLK_SFCXIP>, + <&cru SCLK_SFC>; + pm_qos = <&qos_emmc>, + <&qos_nandc>, + <&qos_sfc>, + <&qos_sdmmc>; + }; + pd_sdio@RV1126_PD_SDIO { + reg = ; + clocks = <&cru HCLK_SDIO>, + <&cru CLK_SDIO>; + pm_qos = <&qos_sdio>; + }; + pd_usb@RV1126_PD_USB { + reg = ; + clocks = <&cru HCLK_USBHOST>, + <&cru HCLK_USBHOST_ARB>, + <&cru CLK_USBHOST_UTMI_OHCI>, + <&cru ACLK_USBOTG>, + <&cru CLK_USBOTG_REF>; + pm_qos = <&qos_usb_host>, + <&qos_usb_otg>; + }; + }; + }; + + i2c0: i2c@ff3f0000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff3f0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c2: i2c@ff400000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff400000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + amba { compatible = "simple-bus"; #address-cells = <1>; @@ -121,12 +464,112 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + dmas = <&dmac 7>, <&dmac 6>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; status = "disabled"; }; + pwm0: pwm@ff430000 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430000 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@ff430010 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430010 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@ff430020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430020 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@ff430030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430030 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_pins>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm4: pwm@ff440000 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff440000 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@ff440010 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff440010 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@ff440020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff440020 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@ff440030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff440030 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pvtm@ff470000 { + compatible = "rockchip,rv1126-pmu-pvtm"; + reg = <0xff470000 0x100>; + clocks = <&pmucru CLK_PMUPVTM>, <&pmucru PCLK_PMUPVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_PMUPVTM>, <&cru SRST_PMUPVTM_P>; + reset-names = "clk", "pclk"; + }; + pmucru: clock-controller@ff480000 { compatible = "rockchip,rv1126-pmucru"; reg = <0xff480000 0x1000>; @@ -141,15 +584,120 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + + assigned-clocks = + <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>, + <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>, + <&cru PLL_HPLL>, <&cru ARMCLK>, + <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>, + <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>, + <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>, + <&cru HCLK_PDCORE_NIU>; + assigned-clock-rates = + <32768>, <1188000000>, + <100000000>, <1000000000>, + <1600000000>, <600000000>, + <500000000>, <200000000>, + <100000000>, <300000000>, + <200000000>, <150000000>, + <200000000>; + assigned-clock-parents = + <&pmucru CLK_OSC0_DIV32K>; }; - fiq_debugger: fiq-debugger { - compatible = "rockchip,fiq-debugger"; - rockchip,serial-id = <2>; - rockchip,wake-irq = <0>; - rockchip,irq-mode-enable = <0>; - rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ - interrupts = ; + i2c1: i2c@ff510000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff510000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c3: i2c@ff520000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff520000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + status = "disabled"; + }; + + i2c4: i2c@ff530000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff530000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + status = "disabled"; + }; + + i2c5: i2c@ff540000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff540000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + status = "disabled"; + }; + + pwm8: pwm@ff550000 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550000 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm9: pwm@ff550010 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550010 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm10: pwm@ff550020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550020 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm11: pwm@ff550030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550030 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; status = "disabled"; }; @@ -159,9 +707,12 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + dmas = <&dmac 5>, <&dmac 4>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; status = "disabled"; }; @@ -171,9 +722,12 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + dmas = <&dmac 9>, <&dmac 8>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; status = "disabled"; }; @@ -183,9 +737,12 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + dmas = <&dmac 11>, <&dmac 10>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>; status = "disabled"; }; @@ -195,9 +752,12 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + dmas = <&dmac 13>, <&dmac 12>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>; status = "disabled"; }; @@ -207,9 +767,388 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + dmas = <&dmac 15>, <&dmac 14>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; status = "disabled"; }; + + cpu_tsadc: tsadc@ff5f0000 { + compatible = "rockchip,rv1126-tsadc"; + reg = <0xff5f0000 0x100>; + interrupts = ; + assigned-clocks = <&cru CLK_CPU_TSADC>; + assigned-clock-rates = <600000>; + clocks = <&cru CLK_CPU_TSADC>, <&cru PCLK_CPU_TSADC>, + <&cru CLK_CPU_TSADCPHY>; + clock-names = "tsadc", "apb_pclk", "phy_clk"; + resets = <&cru SRST_CPU_TSADC_P>, <&cru SRST_CPU_TSADC>, + <&cru SRST_CPU_TSADCPHY>; + reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; + rockchip,hw-tshut-temp = <120000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + npu_tsadc: tsadc@ff5f8000 { + compatible = "rockchip,rv1126-tsadc"; + reg = <0xff5f8000 0x100>; + interrupts = ; + assigned-clocks = <&cru CLK_NPU_TSADC>; + assigned-clock-rates = <600000>; + clocks = <&cru CLK_NPU_TSADC>, <&cru PCLK_NPU_TSADC>, + <&cru CLK_NPU_TSADCPHY>; + clock-names = "tsadc", "apb_pclk", "phy_clk"; + resets = <&cru SRST_NPU_TSADC_P>, <&cru SRST_NPU_TSADC>, + <&cru SRST_NPU_TSADCPHY>; + reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; + rockchip,hw-tshut-temp = <120000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + can: can@ff610000 { + compatible = "rockchip,can-1.0"; + reg = <0xff610000 0x100>; + interrupts = ; + assigned-clocks = <&cru CLK_CAN>; + assigned-clock-rates = <100000000>; + clocks = <&cru CLK_CAN>, <&cru PCLK_CAN>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN>, <&cru SRST_CAN_P>; + reset-names = "can", "can-apb"; + status = "disabled"; + }; + + mailbox: mailbox@ff6a0000 { + compatible = "rockchip,rv1126-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0xff6a0000 0x1000>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + dfi: dfi@ff9c0000 { + reg = <0xff9c0000 0x400>; + compatible = "rockchip,rv1126-dfi"; + rockchip,pmugrf = <&pmugrf>; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rv1126-dmc"; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + ddr_timing = <&ddr_timing>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 924000 + SYS_STATUS_REBOOT 450000 + SYS_STATUS_SUSPEND 328000 + SYS_STATUS_VIDEO_1080P 924000 + SYS_STATUS_BOOST 924000 + SYS_STATUS_ISP 924000 + SYS_STATUS_PERFORMANCE 924000 + >; + auto-min-freq = <328000>; + auto-freq-en = <0>; + #cooling-cells = <2>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + opp-328000000 { + opp-hz = /bits/ 64 <328000000>; + opp-microvolt = <800000>; + }; + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-microvolt = <800000>; + }; + opp-664000000 { + opp-hz = /bits/ 64 <664000000>; + opp-microvolt = <800000>; + }; + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-microvolt = <800000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <800000>; + status = "disabled"; + }; + }; + + vop: vop@ffb00000 { + compatible = "rockchip,rv1126-vop"; + reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; + reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + remote-endpoint = <&rgb_in_vop>; + }; + }; + }; + + vop_mmu: iommu@ffb00f00 { + compatible = "rockchip,iommu"; + reg = <0xffb00f00 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + status = "disabled"; + }; + + rkisp: rkisp@ffb50000 { + compatible = "rockchip,rv1126-rkisp"; + reg = <0xffb50000 0x10000>; + interrupts = , + , + ; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, + <&cru CLK_ISP>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp"; + status = "disabled"; + }; + + rkispp: rkispp@ffb60000 { + compatible = "rockchip,rv1126-rkispp"; + reg = <0xffb60000 0x20000>; + interrupts = , + ; + interrupt-names = "ispp_irq", "fec_irq"; + clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>, + <&cru CLK_ISPP>; + clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; + status = "disabled"; + }; + + pvtm@ffc00000 { + compatible = "rockchip,rv1126-npu-pvtm"; + reg = <0xffc00000 0x100>; + clocks = <&cru CLK_NPUPVTM>, <&cru PCLK_NPUPVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_NPUPVTM>, <&cru SRST_NPUPVTM_P>; + reset-names = "clk", "pclk"; + }; + + gmac: ethernet@ffc40000 { + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; + reg = <0xffc40000 0x0ffff>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru RGMII_MODE_CLK>, <&cru CLK_GMAC_PTPREF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_PDGMAC_NIU_A>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + phy-handle = <&phy>; + status = "disabled"; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "snps,dwmac-mdio"; + phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x0>; + }; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + emmc: dwmmc@ffc50000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc50000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + status = "disabled"; + }; + + sdmmc: dwmmc@ffc60000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc60000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <100000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_det &sdmmc1_bus4>; + status = "disabled"; + }; + + sdio: dwmmc@ffc70000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc70000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>; + status = "disabled"; + }; + + nandc: nandc@ffc80000 { + compatible = "rockchip,rk-nandc"; + reg = <0x0 0xffc80000 0x0 0x4000>; + interrupts = ; + nandc_id = <0>; + clocks = <&cru CLK_NANDC>, <&cru HCLK_NANDC>; + clock-names = "clk_nandc", "hclk_nandc"; + status = "disabled"; + }; + + sfc: sfc@ffc90000 { + compatible = "rockchip,sfc"; + reg = <0xffc90000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <80000000>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1126-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@ff460000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff460000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff620000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff630000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ff640000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff640000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ff650000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff650000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; + +#include "rv1126-pinctrl.dtsi" + diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h new file mode 100644 index 0000000000..b065432e77 --- /dev/null +++ b/include/dt-bindings/clock/rockchip-ddr.h @@ -0,0 +1,63 @@ +/* + * + * Copyright (C) 2017 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H + +#define DDR2_DEFAULT (0) + +#define DDR3_800D (0) /* 5-5-5 */ +#define DDR3_800E (1) /* 6-6-6 */ +#define DDR3_1066E (2) /* 6-6-6 */ +#define DDR3_1066F (3) /* 7-7-7 */ +#define DDR3_1066G (4) /* 8-8-8 */ +#define DDR3_1333F (5) /* 7-7-7 */ +#define DDR3_1333G (6) /* 8-8-8 */ +#define DDR3_1333H (7) /* 9-9-9 */ +#define DDR3_1333J (8) /* 10-10-10 */ +#define DDR3_1600G (9) /* 8-8-8 */ +#define DDR3_1600H (10) /* 9-9-9 */ +#define DDR3_1600J (11) /* 10-10-10 */ +#define DDR3_1600K (12) /* 11-11-11 */ +#define DDR3_1866J (13) /* 10-10-10 */ +#define DDR3_1866K (14) /* 11-11-11 */ +#define DDR3_1866L (15) /* 12-12-12 */ +#define DDR3_1866M (16) /* 13-13-13 */ +#define DDR3_2133K (17) /* 11-11-11 */ +#define DDR3_2133L (18) /* 12-12-12 */ +#define DDR3_2133M (19) /* 13-13-13 */ +#define DDR3_2133N (20) /* 14-14-14 */ +#define DDR3_DEFAULT (21) +#define DDR_DDR2 (22) +#define DDR_LPDDR (23) +#define DDR_LPDDR2 (24) + +#define DDR4_1600J (0) /* 10-10-10 */ +#define DDR4_1600K (1) /* 11-11-11 */ +#define DDR4_1600L (2) /* 12-12-12 */ +#define DDR4_1866L (3) /* 12-12-12 */ +#define DDR4_1866M (4) /* 13-13-13 */ +#define DDR4_1866N (5) /* 14-14-14 */ +#define DDR4_2133N (6) /* 14-14-14 */ +#define DDR4_2133P (7) /* 15-15-15 */ +#define DDR4_2133R (8) /* 16-16-16 */ +#define DDR4_2400P (9) /* 15-15-15 */ +#define DDR4_2400R (10) /* 16-16-16 */ +#define DDR4_2400U (11) /* 18-18-18 */ +#define DDR4_DEFAULT (12) + +#define PAUSE_CPU_STACK_SIZE 16 + +#endif diff --git a/include/dt-bindings/clock/rv1126-cru.h b/include/dt-bindings/clock/rv1126-cru.h index b0fd0fb5c9..291155a9a8 100644 --- a/include/dt-bindings/clock/rv1126-cru.h +++ b/include/dt-bindings/clock/rv1126-cru.h @@ -210,6 +210,8 @@ #define CLK_CORE_NPU 144 #define CLK_CORE_NPUPVTM 145 #define CLK_NPUPVTM 146 +#define SCLK_DDRCLK 147 +#define CLK_OTP 148 /* dclk */ #define DCLK_DECOM 150 @@ -350,8 +352,9 @@ #define PCLK_CSIPHY1 291 #define PCLK_USBPHY_HOST 292 #define PCLK_USBPHY_OTG 293 +#define PCLK_OTP 294 -#define CLK_NR_CLKS (PCLK_USBPHY_OTG + 1) +#define CLK_NR_CLKS (PCLK_OTP + 1) /* pmu soft-reset indices */ diff --git a/include/dt-bindings/memory/rv1126-dram.h b/include/dt-bindings/memory/rv1126-dram.h new file mode 100644 index 0000000000..f33d873a5c --- /dev/null +++ b/include/dt-bindings/memory/rv1126-dram.h @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H + +#define DDR2_DS_FULL (0) +#define DDR2_DS_REDUCE (1) + +#define DDR2_ODT_DIS (0) +#define DDR2_ODT_50ohm (50) /* optional */ +#define DDR2_ODT_75ohm (75) +#define DDR2_ODT_150ohm (150) + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define DDR4_DS_34ohm (34) +#define DDR4_DS_48ohm (48) +#define DDR4_RTT_NOM_DIS (0) +#define DDR4_RTT_NOM_60ohm (60) +#define DDR4_RTT_NOM_120ohm (120) +#define DDR4_RTT_NOM_40ohm (40) +#define DDR4_RTT_NOM_240ohm (240) +#define DDR4_RTT_NOM_48ohm (48) +#define DDR4_RTT_NOM_80ohm (80) +#define DDR4_RTT_NOM_34ohm (34) + +#define PHY_DDR3_RON_DISABLE (0) +#define PHY_DDR3_RON_506ohm (1) +#define PHY_DDR3_RON_253ohm (2) +#define PHY_DDR3_RON_169hm (3) +#define PHY_DDR3_RON_127ohm (4) +#define PHY_DDR3_RON_101ohm (5) +#define PHY_DDR3_RON_84ohm (6) +#define PHY_DDR3_RON_72ohm (7) +#define PHY_DDR3_RON_63ohm (16) +#define PHY_DDR3_RON_56ohm (17) +#define PHY_DDR3_RON_51ohm (18) +#define PHY_DDR3_RON_46ohm (19) +#define PHY_DDR3_RON_42ohm (20) +#define PHY_DDR3_RON_39ohm (21) +#define PHY_DDR3_RON_36ohm (22) +#define PHY_DDR3_RON_34ohm (23) +#define PHY_DDR3_RON_32ohm (24) +#define PHY_DDR3_RON_30ohm (25) +#define PHY_DDR3_RON_28ohm (26) +#define PHY_DDR3_RON_27ohm (27) +#define PHY_DDR3_RON_25ohm (28) +#define PHY_DDR3_RON_24ohm (29) +#define PHY_DDR3_RON_23ohm (30) +#define PHY_DDR3_RON_22ohm (31) + +#define PHY_DDR3_RTT_DISABLE (0) +#define PHY_DDR3_RTT_953ohm (1) +#define PHY_DDR3_RTT_483ohm (2) +#define PHY_DDR3_RTT_320ohm (3) +#define PHY_DDR3_RTT_241ohm (4) +#define PHY_DDR3_RTT_193ohm (5) +#define PHY_DDR3_RTT_161ohm (6) +#define PHY_DDR3_RTT_138ohm (7) +#define PHY_DDR3_RTT_121ohm (16) +#define PHY_DDR3_RTT_107ohm (17) +#define PHY_DDR3_RTT_97ohm (18) +#define PHY_DDR3_RTT_88ohm (19) +#define PHY_DDR3_RTT_80ohm (20) +#define PHY_DDR3_RTT_74ohm (21) +#define PHY_DDR3_RTT_69ohm (22) +#define PHY_DDR3_RTT_64ohm (23) +#define PHY_DDR3_RTT_60ohm (24) +#define PHY_DDR3_RTT_57ohm (25) +#define PHY_DDR3_RTT_54ohm (26) +#define PHY_DDR3_RTT_51ohm (27) +#define PHY_DDR3_RTT_48ohm (28) +#define PHY_DDR3_RTT_46ohm (29) +#define PHY_DDR3_RTT_44ohm (30) +#define PHY_DDR3_RTT_42ohm (31) + +#define PHY_DDR4_LPDDR3_RON_DISABLE (0) +#define PHY_DDR4_LPDDR3_RON_570ohm (1) +#define PHY_DDR4_LPDDR3_RON_285ohm (2) +#define PHY_DDR4_LPDDR3_RON_190ohm (3) +#define PHY_DDR4_LPDDR3_RON_142ohm (4) +#define PHY_DDR4_LPDDR3_RON_114ohm (5) +#define PHY_DDR4_LPDDR3_RON_95ohm (6) +#define PHY_DDR4_LPDDR3_RON_81ohm (7) +#define PHY_DDR4_LPDDR3_RON_71ohm (16) +#define PHY_DDR4_LPDDR3_RON_63ohm (17) +#define PHY_DDR4_LPDDR3_RON_57ohm (18) +#define PHY_DDR4_LPDDR3_RON_52ohm (19) +#define PHY_DDR4_LPDDR3_RON_47ohm (20) +#define PHY_DDR4_LPDDR3_RON_44ohm (21) +#define PHY_DDR4_LPDDR3_RON_41ohm (22) +#define PHY_DDR4_LPDDR3_RON_38ohm (23) +#define PHY_DDR4_LPDDR3_RON_36ohm (24) +#define PHY_DDR4_LPDDR3_RON_34ohm (25) +#define PHY_DDR4_LPDDR3_RON_32ohm (26) +#define PHY_DDR4_LPDDR3_RON_30ohm (27) +#define PHY_DDR4_LPDDR3_RON_28ohm (28) +#define PHY_DDR4_LPDDR3_RON_27ohm (29) +#define PHY_DDR4_LPDDR3_RON_26ohm (30) +#define PHY_DDR4_LPDDR3_RON_25ohm (31) + +#define PHY_DDR4_LPDDR3_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_RTT_973ohm (1) +#define PHY_DDR4_LPDDR3_RTT_493ohm (2) +#define PHY_DDR4_LPDDR3_RTT_327ohm (3) +#define PHY_DDR4_LPDDR3_RTT_247ohm (4) +#define PHY_DDR4_LPDDR3_RTT_197ohm (5) +#define PHY_DDR4_LPDDR3_RTT_164ohm (6) +#define PHY_DDR4_LPDDR3_RTT_141ohm (7) +#define PHY_DDR4_LPDDR3_RTT_123ohm (16) +#define PHY_DDR4_LPDDR3_RTT_109ohm (17) +#define PHY_DDR4_LPDDR3_RTT_99ohm (18) +#define PHY_DDR4_LPDDR3_RTT_90ohm (19) +#define PHY_DDR4_LPDDR3_RTT_82ohm (20) +#define PHY_DDR4_LPDDR3_RTT_76ohm (21) +#define PHY_DDR4_LPDDR3_RTT_70ohm (22) +#define PHY_DDR4_LPDDR3_RTT_66ohm (23) +#define PHY_DDR4_LPDDR3_RTT_62ohm (24) +#define PHY_DDR4_LPDDR3_RTT_58ohm (25) +#define PHY_DDR4_LPDDR3_RTT_55ohm (26) +#define PHY_DDR4_LPDDR3_RTT_52ohm (27) +#define PHY_DDR4_LPDDR3_RTT_49ohm (28) +#define PHY_DDR4_LPDDR3_RTT_47ohm (29) +#define PHY_DDR4_LPDDR3_RTT_45ohm (30) +#define PHY_DDR4_LPDDR3_RTT_43ohm (31) + +#define PHY_LPDDR4_RON_DISABLE (0) +#define PHY_LPDDR4_RON_606ohm (1) +#define PHY_LPDDR4_RON_303ohm (2) +#define PHY_LPDDR4_RON_202ohm (3) +#define PHY_LPDDR4_RON_152ohm (4) +#define PHY_LPDDR4_RON_121ohm (5) +#define PHY_LPDDR4_RON_101ohm (6) +#define PHY_LPDDR4_RON_87ohm (7) +#define PHY_LPDDR4_RON_76ohm (16) +#define PHY_LPDDR4_RON_67ohm (17) +#define PHY_LPDDR4_RON_61ohm (18) +#define PHY_LPDDR4_RON_55ohm (19) +#define PHY_LPDDR4_RON_51ohm (20) +#define PHY_LPDDR4_RON_47ohm (21) +#define PHY_LPDDR4_RON_43ohm (22) +#define PHY_LPDDR4_RON_40ohm (23) +#define PHY_LPDDR4_RON_38ohm (24) +#define PHY_LPDDR4_RON_36ohm (25) +#define PHY_LPDDR4_RON_34ohm (26) +#define PHY_LPDDR4_RON_32ohm (27) +#define PHY_LPDDR4_RON_30ohm (28) +#define PHY_LPDDR4_RON_29ohm (29) +#define PHY_LPDDR4_RON_28ohm (30) +#define PHY_LPDDR4_RON_26ohm (31) + +#define PHY_LPDDR4_RTT_DISABLE (0) +#define PHY_LPDDR4_RTT_998ohm (1) +#define PHY_LPDDR4_RTT_506ohm (2) +#define PHY_LPDDR4_RTT_336ohm (3) +#define PHY_LPDDR4_RTT_253ohm (4) +#define PHY_LPDDR4_RTT_202ohm (5) +#define PHY_LPDDR4_RTT_169ohm (6) +#define PHY_LPDDR4_RTT_144ohm (7) +#define PHY_LPDDR4_RTT_127ohm (16) +#define PHY_LPDDR4_RTT_112ohm (17) +#define PHY_LPDDR4_RTT_101ohm (18) +#define PHY_LPDDR4_RTT_92ohm (19) +#define PHY_LPDDR4_RTT_84ohm (20) +#define PHY_LPDDR4_RTT_78ohm (21) +#define PHY_LPDDR4_RTT_72ohm (22) +#define PHY_LPDDR4_RTT_67ohm (23) +#define PHY_LPDDR4_RTT_63ohm (24) +#define PHY_LPDDR4_RTT_60ohm (25) +#define PHY_LPDDR4_RTT_56ohm (26) +#define PHY_LPDDR4_RTT_53ohm (27) +#define PHY_LPDDR4_RTT_51ohm (28) +#define PHY_LPDDR4_RTT_48ohm (29) +#define PHY_LPDDR4_RTT_46ohm (30) +#define PHY_LPDDR4_RTT_44ohm (31) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H*/ diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h new file mode 100644 index 0000000000..3e21010364 --- /dev/null +++ b/include/dt-bindings/power/rv1126-power.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__ +#define __DT_BINDINGS_POWER_RV1126_POWER_H__ + +/* VD_CORE */ +#define RV1126_PD_CPU_0 0 +#define RV1126_PD_CPU_1 1 +#define RV1126_PD_CPU_2 2 +#define RV1126_PD_CPU_3 3 +#define RV1126_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RV1126_PD_PMU 5 +#define RV1126_PD_PMU_ALIVE 6 + +/* VD_NPU */ +#define RV1126_PD_NPU 7 + +/* VD_VEPU */ +#define RV1126_PD_VEPU 8 + +/* VD_LOGIC */ +#define RV1126_PD_VI 9 +#define RV1126_PD_VO 10 +#define RV1126_PD_ISPP 11 +#define RV1126_PD_VDPU 12 +#define RV1126_PD_CRYPTO 13 +#define RV1126_PD_DDR 14 +#define RV1126_PD_NVM 15 +#define RV1126_PD_SDIO 16 +#define RV1126_PD_USB 17 +#define RV1126_PD_LOGIC_ALIVE 18 + +#endif diff --git a/include/dt-bindings/soc/rockchip-system-status.h b/include/dt-bindings/soc/rockchip-system-status.h new file mode 100644 index 0000000000..fe103a55f2 --- /dev/null +++ b/include/dt-bindings/soc/rockchip-system-status.h @@ -0,0 +1,43 @@ +/* + * + * Copyright (C) 2017 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H +#define _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H + +#define SYS_STATUS_NORMAL (1 << 0) +#define SYS_STATUS_SUSPEND (1 << 1) +#define SYS_STATUS_IDLE (1 << 2) +#define SYS_STATUS_REBOOT (1 << 3) +#define SYS_STATUS_VIDEO_4K (1 << 4) +#define SYS_STATUS_VIDEO_1080P (1 << 5) +#define SYS_STATUS_GPU (1 << 6) +#define SYS_STATUS_RGA (1 << 7) +#define SYS_STATUS_CIF0 (1 << 8) +#define SYS_STATUS_CIF1 (1 << 9) +#define SYS_STATUS_LCDC0 (1 << 10) +#define SYS_STATUS_LCDC1 (1 << 11) +#define SYS_STATUS_BOOST (1 << 12) +#define SYS_STATUS_PERFORMANCE (1 << 13) +#define SYS_STATUS_ISP (1 << 14) +#define SYS_STATUS_HDMI (1 << 15) +#define SYS_STATUS_VIDEO_4K_10B (1 << 16) +#define SYS_STATUS_LOW_POWER (1 << 17) + +#define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_4K | \ + SYS_STATUS_VIDEO_1080P | \ + SYS_STATUS_VIDEO_4K_10B) +#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0 | SYS_STATUS_LCDC1) + +#endif