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clk: rockchip: rk3288: support aclk_vop freq setting 

Change-Id: Ifb595f244608378bff1e6443dfc017418f28ce2a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-10-29 11:04:35 +08:00 committed by Jianhong Chen
parent 78d830ca5b
commit 5a616fcf52
2 changed files with 36 additions and 26 deletions
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15
arch/arm/include/asm/arch-rockchip/cru_rk3288.h
View File

@ -155,6 +155,21 @@ enum {
DCLK_VOP1_SELECT_NPLL = 2,
};
/* CRU_CLKSEL31_CON */
enum {
ACLK_VOP_SELECT_CPLL = 0,
ACLK_VOP_SELECT_GPLL = 1,
ACLK_VOP_SELECT_USB480 = 2,
ACLK_VOP1_PLL_SHIFT = 14,
ACLK_VOP1_PLL_MASK = 3 << ACLK_VOP1_PLL_SHIFT,
ACLK_VOP1_DIV_SHIFT = 8,
ACLK_VOP1_DIV_MASK = 0x1f << ACLK_VOP1_DIV_SHIFT,
ACLK_VOP0_PLL_SHIFT = 6,
ACLK_VOP0_PLL_MASK = 3 << ACLK_VOP0_PLL_SHIFT,
ACLK_VOP0_DIV_SHIFT = 0,
ACLK_VOP0_DIV_MASK = 0x1f << ACLK_VOP0_DIV_SHIFT,
};
/* CRU_CLKSEL37_CON */
enum {
PCLK_CORE_DBG_DIV_SHIFT = 9,

47
drivers/clk/rockchip/clk_rk3288.c
View File

@ -379,7 +379,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
struct pll_div cpll_config = {0};
u32 lcdc_div, parent;
int ret;
unsigned int gpll_rate, npll_rate;
unsigned int gpll_rate, npll_rate, cpll_rate;
gpll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
npll_rate = rkclk_pll_get_rate(cru, CLK_NEW);
@ -387,7 +387,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
/* vop dclk source clk: cpll,dclk_div: 1 */
switch (periph) {
case DCLK_VOP0:
ret = (readl(&cru->cru_clksel_con[27]) && DCLK_VOP0_PLL_MASK) >>
ret = (readl(&cru->cru_clksel_con[27]) & DCLK_VOP0_PLL_MASK) >>
DCLK_VOP0_PLL_SHIFT;
if (ret == DCLK_VOP0_SELECT_CPLL) {
ret = pll_para_config(rate_hz, &cpll_config, &lcdc_div);
@ -424,7 +424,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
(parent << DCLK_VOP0_PLL_SHIFT));
break;
case DCLK_VOP1:
ret = (readl(&cru->cru_clksel_con[29]) && DCLK_VOP1_PLL_MASK) >>
ret = (readl(&cru->cru_clksel_con[29]) & DCLK_VOP1_PLL_MASK) >>
DCLK_VOP1_PLL_SHIFT;
if (ret == DCLK_VOP1_SELECT_CPLL) {
ret = pll_para_config(rate_hz, &cpll_config, &lcdc_div);
@ -461,6 +461,22 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
((lcdc_div - 1) << DCLK_VOP1_DIV_SHIFT) |
(parent << DCLK_VOP1_PLL_SHIFT));
break;
case ACLK_VOP0:
cpll_rate = rkclk_pll_get_rate(cru, CLK_CODEC);
lcdc_div = DIV_ROUND_UP(cpll_rate, rate_hz);
rk_clrsetreg(&cru->cru_clksel_con[31],
ACLK_VOP0_PLL_MASK | ACLK_VOP0_DIV_MASK,
ACLK_VOP_SELECT_CPLL << ACLK_VOP0_PLL_SHIFT |
(lcdc_div - 1) << ACLK_VOP0_DIV_SHIFT);
break;
case ACLK_VOP1:
cpll_rate = rkclk_pll_get_rate(cru, CLK_CODEC);
lcdc_div = DIV_ROUND_UP(cpll_rate, rate_hz);
rk_clrsetreg(&cru->cru_clksel_con[31],
ACLK_VOP1_PLL_MASK | ACLK_VOP1_DIV_MASK,
ACLK_VOP_SELECT_CPLL << ACLK_VOP1_PLL_SHIFT |
(lcdc_div - 1) << ACLK_VOP1_DIV_SHIFT);
break;
}
return 0;
@ -865,6 +881,8 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
break;
case DCLK_VOP0:
case DCLK_VOP1:
case ACLK_VOP0:
case ACLK_VOP1:
new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
break;
case SCLK_EDP_24M:
@ -877,29 +895,6 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
new_rate = rate;
break;
case ACLK_VOP0:
case ACLK_VOP1: {
u32 div;
/* vop aclk source clk: cpll */
div = CPLL_HZ / rate;
assert((div - 1 < 64) && (div * rate == CPLL_HZ));
switch (clk->id) {
case ACLK_VOP0:
rk_clrsetreg(&cru->cru_clksel_con[31],
3 << 6 | 0x1f << 0,
0 << 6 | (div - 1) << 0);
break;
case ACLK_VOP1:
rk_clrsetreg(&cru->cru_clksel_con[31],
3 << 14 | 0x1f << 8,
0 << 14 | (div - 1) << 8);
break;
}
new_rate = rate;
break;
}
case PCLK_HDMI_CTRL:
/* enable pclk hdmi ctrl */
rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);