drm/rockchip: vop: add support rk3308 vop
Change-Id: I067ac3f95163dd678317a11ffad7a7d85225c9ee Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
Kever Yang
parent
45fa51f320
commit
5c651246bb
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@ -65,6 +65,23 @@
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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status = "disabled";
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route {
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route_rgb: route-rgb {
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status = "okay";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vop_out_rgb>;
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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@ -164,6 +181,27 @@
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status = "disabled";
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};
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vop: vop@ff2e0000 {
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compatible = "rockchip,rk3308-vop";
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reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>;
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reg-names = "regs", "gamma_lut";
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>,
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<&cru HCLK_VOP>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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status = "disabled";
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vop_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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vop_out_rgb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&rgb_in_vop>;
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};
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};
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};
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pwm0: pwm@ff180000 {
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compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xff180000 0x0 0x10>;
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@ -208,6 +246,31 @@
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status = "disabled";
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};
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rgb: rgb {
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compatible = "rockchip,rk3308-rgb";
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&lcdc_ctl>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgb_in_vop: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vop_out_rgb>;
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};
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};
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};
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};
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saradc: saradc@ff1e0000 {
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compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
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reg = <0x0 0xff1e0000 0x0 0x100>;
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@ -951,5 +1014,55 @@
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<1 RK_PB4 3 &pcfg_pull_none>;
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};
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};
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lcdc {
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lcdc_ctl: lcdc-ctl {
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rockchip,pins =
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/* dclk */
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<1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
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/* hsync */
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<1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,
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/* vsync */
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<1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
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/* den */
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<1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
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/* d0 */
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<1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
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/* d1 */
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<1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
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/* d2 */
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<1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
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/* d3 */
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<1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
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/* d4 */
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<1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
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/* d5 */
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<1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
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/* d6 */
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<1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
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/* d7 */
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<1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
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/* d8 */
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<1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
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/* d9 */
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<1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
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/* d10 */
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<1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
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/* d11 */
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<1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
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/* d12 */
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<1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
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/* d13 */
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<1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
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/* d14 */
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<1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,
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/* d15 */
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<1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
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/* d16 */
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<1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
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/* d17 */
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<1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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};
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};
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@ -55,6 +55,11 @@ CONFIG_USB_GADGET_DOWNLOAD=y
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CONFIG_G_DNL_MANUFACTURER="Rockchip"
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CONFIG_G_DNL_VENDOR_NUM=0x2207
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CONFIG_G_DNL_PRODUCT_NUM=0x330d
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CONFIG_DM_VIDEO=y
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CONFIG_DISPLAY=y
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CONFIG_DRM_ROCKCHIP=y
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CONFIG_DRM_ROCKCHIP_RGB=y
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CONFIG_LCD=y
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CONFIG_USE_TINY_PRINTF=y
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_ERRNO_STR=y
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@ -32,6 +32,11 @@ static const struct rockchip_crtc px30_vop_big_data = {
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.data = &px30_vop_big,
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};
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static const struct rockchip_crtc rk3308_vop_data = {
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.funcs = &rockchip_vop_funcs,
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.data = &rk3308_vop,
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};
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static const struct rockchip_crtc rk3288_vop_big_data = {
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.funcs = &rockchip_vop_funcs,
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.data = &rk3288_vop_big,
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@ -85,6 +90,9 @@ static const struct udevice_id rockchip_vop_ids[] = {
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}, {
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.compatible = "rockchip,px30-vop-big",
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.data = (ulong)&px30_vop_big_data,
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}, {
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.compatible = "rockchip,rk3308-vop",
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.data = (ulong)&rk3308_vop_data,
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}, {
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.compatible = "rockchip,rk3288-vop-big",
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.data = (ulong)&rk3288_vop_big_data,
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@ -28,6 +28,7 @@ extern const struct rockchip_crtc_funcs rockchip_vop_funcs;
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extern const struct vop_data rk3036_vop;
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extern const struct vop_data px30_vop_lit;
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extern const struct vop_data px30_vop_big;
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extern const struct vop_data rk3308_vop;
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extern const struct vop_data rk3288_vop_big;
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extern const struct vop_data rk3288_vop_lit;
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extern const struct vop_data rk3368_vop;
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@ -502,3 +502,70 @@ const struct vop_data px30_vop_big = {
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.line_flag = &rk3366_vop_lite_line_flag,
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.reg_len = RK3366_LIT_FRC_LOWER01_0 * 4,
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};
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static const struct vop_ctrl rk3308_ctrl_data = {
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.standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
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.axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
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.axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
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.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
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.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
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.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
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.vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
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.vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
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.vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
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.global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
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.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
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.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 3),
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.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
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.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
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.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
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.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
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.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
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.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
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.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
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.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
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.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
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.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
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.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
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.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
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.dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
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.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
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.dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
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.cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
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.bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
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.bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
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.bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
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.bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
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.bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
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.bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
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.bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
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.bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
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.bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
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.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
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.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
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.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
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.mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
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.mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
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.mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
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.mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
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.mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
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.mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
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.mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
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.mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
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.mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
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.mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
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.mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
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.mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT,
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0xffffffff, 0),
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};
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const struct vop_data rk3308_vop = {
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.version = VOP_VERSION(2, 7),
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.max_output = {1920, 1080},
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.ctrl = &rk3308_ctrl_data,
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.win = &rk3366_win0_data,
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.line_flag = &rk3366_vop_lite_line_flag,
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.reg_len = RK3366_LIT_FRC_LOWER01_0 * 4,
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};
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@ -12,6 +12,10 @@
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define ROCKCHIP_DEVICE_SETTINGS \
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"stdout=serial,vidconsole\0" \
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"stderr=serial,vidconsole\0"
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#undef CONFIG_CONSOLE_SCROLL_LINES
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#define CONFIG_CONSOLE_SCROLL_LINES 10
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#undef CONFIG_BOOTCOMMAND
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@ -59,6 +59,7 @@
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ENV_MEM_LAYOUT_SETTINGS \
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"partitions=" PARTS_DEFAULT \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif
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