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mmc: dw_mmc: set DWMCI_MSIZE to 6 

We set the fifo_depth to 0x100 word in Rockchip platform, and
fifo_depth/2 must be multiple of dma_multiple_transaction_size.
So we can set DWMCI_MSIZE to 6 according to max
dma_multiple_transaction_size being 128.

The DWMCI_MSIZE must be set as larger as possible. If not, dma fifo will
be full, and crc error occur when the clock stop during the data phase.

Change-Id: I013b6f9c272edbc723b2f627e88d30d653c42d1b
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
This commit is contained in:
Jason Zhu 2018-08-21 17:55:32 +08:00 committed by Kever Yang
parent c30b51158f
commit 5ef8980810
3 changed files with 9 additions and 2 deletions
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3
drivers/mmc/dw_mmc.c
View File

@ -611,7 +611,8 @@ static int dwmci_init(struct mmc *mmc)
fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
host->fifoth_val = MSIZE(DWMCI_MSIZE) |
RX_WMARK(fifo_size / 2 - 1) |
TX_WMARK(fifo_size / 2);
}
dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);

2
drivers/mmc/rockchip_dw_mmc.c
View File

@ -186,7 +186,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
debug("MMC: sample clock not found, not support hs200!\n");
host->execute_tuning = rockchip_dwmmc_execute_tuning;
#endif
host->fifoth_val = MSIZE(0x2) |
host->fifoth_val = MSIZE(DWMCI_MSIZE) |
RX_WMARK(priv->fifo_depth / 2 - 1) |
TX_WMARK(priv->fifo_depth / 2);

6
include/dwmmc.h
View File

@ -135,6 +135,12 @@
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
/*
* DWMCI_MSIZE is uses to set burst size of multiple transaction.
* The burst size is set to 128 if DWMCI_MSIZE is set to 0x6.
*/
#define DWMCI_MSIZE 0x6
/**
* struct dwmci_host - Information about a designware MMC host
*