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rockchip: irq: enable GICv2 on px30 

Change-Id: I797fa071091f6856c3a7eef6ae6a9f0c4bcb377a
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This commit is contained in:
Joseph Chen 2018-02-06 15:21:07 +08:00 committed by Kever Yang
parent 0c05cc9580
commit 6084810988
3 changed files with 24 additions and 2 deletions
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1
arch/arm/mach-rockchip/Kconfig
View File

@ -3,6 +3,7 @@ if ARCH_ROCKCHIP
config ROCKCHIP_PX30
bool "Support Rockchip PX30"
select ARM64
select GICV2
help
The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
including NEON and GPU, Mali-400 graphics, several DDR3 options

4
include/configs/px30_common.h
View File

@ -29,8 +29,8 @@
#define COUNTER_FREQUENCY 24000000
#define GICD_BASE 0xFF811000
#define GICC_BASE 0xFF812000
#define GICD_BASE 0xff131000
#define GICC_BASE 0xff132000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */

21
include/irq-platform.h
View File

@ -131,6 +131,27 @@
#define GPIO_BANK_NUM 5
#define GPIO_BANK_PINS 32
#elif defined(CONFIG_ROCKCHIP_PX30)
#define GPIO0_PHYS 0xff040000
#define GPIO1_PHYS 0xff250000
#define GPIO2_PHYS 0xff260000
#define GPIO3_PHYS 0xff270000
#define IRQ_GPIO0 35
#define IRQ_GPIO1 36
#define IRQ_GPIO2 37
#define IRQ_GPIO3 38
#define IRQ_PWM0 56
#define IRQ_PWM1 57
#define IRQ_TIMER1 63 /* non-secure */
#define GIC_IRQS_NR (4 * 32)
#define GPIO_IRQS_NR (4 * 32)
#define GPIO_BANK_NUM 4
#define GPIO_BANK_PINS 32
#else
"Missing define RIQ relative things"
#endif