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rockchip: enable SYS_NS16550 for all SoCs by default 

All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.

Change-Id: I4be3a801bf5537b94ed0c100cb44f49d78b8b15a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2018-01-20 21:43:05 +08:00
parent 2d2f5f9a1f
commit 60b9259c7e
13 changed files with 4 additions and 23 deletions
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1
arch/arm/Kconfig
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@ -1131,6 +1131,7 @@ config ARCH_ROCKCHIP
select DM_REGULATOR select DM_REGULATOR
select CMD_ROCKUSB if USB_GADGET_DOWNLOAD select CMD_ROCKUSB if USB_GADGET_DOWNLOAD
select ENABLE_ARM_SOC_BOOT0_HOOK select ENABLE_ARM_SOC_BOOT0_HOOK
select SYS_NS16550
imply CMD_FASTBOOT imply CMD_FASTBOOT
imply FASTBOOT imply FASTBOOT
imply FAT_WRITE imply FAT_WRITE

2
arch/arm/mach-rockchip/Kconfig
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@ -120,7 +120,6 @@ config ROCKCHIP_RK3328
imply TPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT
imply SPL_SEPARATE_BSS imply SPL_SEPARATE_BSS
select DEBUG_UART_BOARD_INIT select DEBUG_UART_BOARD_INIT
select SYS_NS16550
help help
The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
@ -155,7 +154,6 @@ config ROCKCHIP_RK3368
imply SPL_SERIAL_SUPPORT imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT
select DEBUG_UART_BOARD_INIT select DEBUG_UART_BOARD_INIT
select SYS_NS16550
select GICV2 select GICV2
help help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised

3
include/configs/rk3036_common.h
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@ -18,9 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x60000000 #define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SYS_LOAD_ADDR 0x60800800

1
include/configs/rk3066_common.h
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@ -30,7 +30,6 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x78000000 #define CONFIG_SYS_INIT_SP_ADDR 0x78000000
#define CONFIG_SYS_LOAD_ADDR 0x70800800 #define CONFIG_SYS_LOAD_ADDR 0x70800800
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_BOUNCE_BUFFER #define CONFIG_BOUNCE_BUFFER
#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_FRAMEWORK

2
include/configs/rk3128_common.h
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@ -19,8 +19,6 @@
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x60000000 #define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SYS_LOAD_ADDR 0x60800800

2
include/configs/rk3188_common.h
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@ -22,8 +22,6 @@
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_NS16550_MEM32
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
#define CONFIG_SYS_TEXT_BASE 0x60000000 #define CONFIG_SYS_TEXT_BASE 0x60000000

1
include/configs/rk322x_common.h
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@ -19,7 +19,6 @@
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x61000000 #define CONFIG_SYS_TEXT_BASE 0x61000000
#define CONFIG_SYS_INIT_SP_ADDR 0x61100000 #define CONFIG_SYS_INIT_SP_ADDR 0x61100000
#define CONFIG_SYS_LOAD_ADDR 0x61800800 #define CONFIG_SYS_LOAD_ADDR 0x61800800

2
include/configs/rk3288_common.h
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@ -20,8 +20,6 @@
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x0 once return from SPL */ /* Bootrom will load u-boot binary to 0x0 once return from SPL */
#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_TEXT_BASE 0x00000000

2
include/configs/rk3328_common.h
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@ -15,8 +15,6 @@
#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x00200000 #define CONFIG_SYS_TEXT_BASE 0x00200000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SYS_LOAD_ADDR 0x00800800

4
include/configs/rk3368_common.h
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@ -22,13 +22,11 @@
#define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x00200000 #define CONFIG_SYS_TEXT_BASE 0x00200000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00280000 #define CONFIG_SYS_LOAD_ADDR 0x00280000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x00000000 #define CONFIG_SPL_TEXT_BASE 0x00000000
#define CONFIG_SPL_MAX_SIZE 0x40000 #define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x400000 #define CONFIG_SPL_BSS_START_ADDR 0x400000

2
include/configs/rk3399_common.h
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@ -18,8 +18,6 @@
#define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_LOAD
#endif #endif
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x00200000 #define CONFIG_SYS_TEXT_BASE 0x00200000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SYS_LOAD_ADDR 0x00800800

2
include/configs/rockchip-common.h
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@ -12,6 +12,8 @@
#define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_NS16550_MEM32
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h> #include <config_distro_defaults.h>

3
include/configs/rv1108_common.h
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@ -18,9 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x10350020 #define CONFIG_SYS_TIMER_BASE 0x10350020
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE