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clk: rockchip: rv1126: mux aclk_pdbus according to frequency 

Aim to reduce power consumption, cpll should be gated and the clocks
will mux to non-cpll.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: If9d1b48cdb237cf38133523a4fc20fa6e87e8e62
This commit is contained in:
Ziyuan Xu 2020-12-10 18:17:43 +08:00 committed by Jianhong Chen
parent 9db037e4cc
commit 658285c1fb
1 changed files with 9 additions and 3 deletions
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12
drivers/clk/rockchip/clk_rv1126.c
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@ -668,15 +668,21 @@ static ulong rv1126_pdbus_set_clk(struct rv1126_clk_priv *priv, ulong clk_id,
ulong rate)
{
struct rv1126_cru *cru = priv->cru;
int src_clk_div;
int src_clk_div, clk_sel;
switch (clk_id) {
case ACLK_PDBUS:
src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
if (CPLL_HZ % rate) {
src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
clk_sel = ACLK_PDBUS_SEL_GPLL;
} else {
src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
clk_sel = ACLK_PDBUS_SEL_CPLL;
}
assert(src_clk_div - 1 <= 31);
rk_clrsetreg(&cru->clksel_con[2],
ACLK_PDBUS_SEL_MASK | ACLK_PDBUS_DIV_MASK,
ACLK_PDBUS_SEL_CPLL << ACLK_PDBUS_SEL_SHIFT |
clk_sel << ACLK_PDBUS_SEL_SHIFT |
(src_clk_div - 1) << ACLK_PDBUS_DIV_SHIFT);
break;
case HCLK_PDBUS: