From 658285c1fb7886da12b18e81a5b61c23bf7b8679 Mon Sep 17 00:00:00 2001 From: Ziyuan Xu Date: Thu, 10 Dec 2020 18:17:43 +0800 Subject: [PATCH] clk: rockchip: rv1126: mux aclk_pdbus according to frequency Aim to reduce power consumption, cpll should be gated and the clocks will mux to non-cpll. Signed-off-by: Ziyuan Xu Change-Id: If9d1b48cdb237cf38133523a4fc20fa6e87e8e62 --- drivers/clk/rockchip/clk_rv1126.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c index fdbd645dd5..ad3915534c 100644 --- a/drivers/clk/rockchip/clk_rv1126.c +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -668,15 +668,21 @@ static ulong rv1126_pdbus_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, ulong rate) { struct rv1126_cru *cru = priv->cru; - int src_clk_div; + int src_clk_div, clk_sel; switch (clk_id) { case ACLK_PDBUS: - src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + if (CPLL_HZ % rate) { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + clk_sel = ACLK_PDBUS_SEL_GPLL; + } else { + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + clk_sel = ACLK_PDBUS_SEL_CPLL; + } assert(src_clk_div - 1 <= 31); rk_clrsetreg(&cru->clksel_con[2], ACLK_PDBUS_SEL_MASK | ACLK_PDBUS_DIV_MASK, - ACLK_PDBUS_SEL_CPLL << ACLK_PDBUS_SEL_SHIFT | + clk_sel << ACLK_PDBUS_SEL_SHIFT | (src_clk_div - 1) << ACLK_PDBUS_DIV_SHIFT); break; case HCLK_PDBUS: