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clk: rockchip: rk1808: support pclk_wdt get rate 

Change-Id: Ib204b4c014c3b4cbd35d1f335378b0b399689303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-04-09 17:35:43 +08:00
parent 8afd7ff1e3
commit 68d8964cb4
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/rockchip/clk_rk1808.c
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@ -583,6 +583,7 @@ static ulong rk1808_bus_get_clk(struct rk1808_clk_priv *priv, ulong clk_id)
parent = priv->gpll_hz;
break;
case LSCLK_BUS_PRE:
case PCLK_WDT:
con = readl(&cru->clksel_con[28]);
div = (con & LSCLK_BUS_DIV_CON_MASK) >> LSCLK_BUS_DIV_CON_SHIFT;
parent = priv->gpll_hz;
@ -822,6 +823,7 @@ static ulong rk1808_clk_get_rate(struct clk *clk)
case HSCLK_BUS_PRE:
case MSCLK_BUS_PRE:
case LSCLK_BUS_PRE:
case PCLK_WDT:
rate = rk1808_bus_get_clk(priv, clk->id);
break;
case MSCLK_PERI: