net: gmac_rockchip: Add dwc_eth_qos support
Change the original data structure so that Rockchip's Soc gmac controller can support the designware.c and dwc_eth_qos.c drivers, a Soc can only support one. Signed-off-by: David Wu <david.wu@rock-chips.com> Change-Id: I313674274fc2eddb7717ba76c537cd668d6a492b
This commit is contained in:
David Wu
Joseph Chen
parent
a494aeaa44
commit
6f0a52e952
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@ -276,7 +276,7 @@ config PIC32_ETH
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config GMAC_ROCKCHIP
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bool "Rockchip Synopsys Designware Ethernet MAC"
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depends on DM_ETH && ETH_DESIGNWARE
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depends on DM_ETH && (ETH_DESIGNWARE || DWC_ETH_QOS)
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help
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This driver provides Rockchip SoCs network support based on the
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Synopsys Designware driver.
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@ -15,6 +15,9 @@
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#include <asm/arch/periph.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#ifdef CONFIG_DWC_ETH_QOS
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#include "dwc_eth_qos.h"
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#else
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#include <asm/arch/grf_px30.h>
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#include <asm/arch/grf_rk1808.h>
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#include <asm/arch/grf_rk322x.h>
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@ -24,26 +27,42 @@
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#include <asm/arch/grf_rk3368.h>
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#include <asm/arch/grf_rk3399.h>
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#include <asm/arch/grf_rv1108.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include "designware.h"
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#include <dt-bindings/clock/rk3288-cru.h>
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#endif
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rockchip_eth_dev {
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#ifdef CONFIG_DWC_ETH_QOS
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struct eqos_priv eqos;
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#else
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struct dw_eth_dev dw;
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#endif
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};
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/*
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* Platform data for the gmac
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*
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* dw_eth_pdata: Required platform data for designware driver (must be first)
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*/
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struct gmac_rockchip_platdata {
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#ifndef CONFIG_DWC_ETH_QOS
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struct dw_eth_pdata dw_eth_pdata;
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#else
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struct eth_pdata eth_pdata;
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#endif
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bool clock_input;
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int tx_delay;
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int rx_delay;
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};
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struct rk_gmac_ops {
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int (*fix_mac_speed)(struct dw_eth_dev *priv);
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#ifdef CONFIG_DWC_ETH_QOS
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const struct eqos_config config;
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#endif
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int (*fix_mac_speed)(struct rockchip_eth_dev *dev);
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void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
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void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
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};
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@ -81,11 +100,17 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
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if (pdata->rx_delay == -ENOENT)
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pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
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#ifdef CONFIG_DWC_ETH_QOS
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return 0;
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#else
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return designware_eth_ofdata_to_platdata(dev);
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#endif
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}
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static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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#ifndef CONFIG_DWC_ETH_QOS
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static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
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{
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struct dw_eth_dev *priv = &dev->dw;
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struct px30_grf *grf;
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struct clk clk_speed;
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int speed, ret;
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@ -125,8 +150,9 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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return 0;
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}
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static int rk1808_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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static int rk1808_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
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{
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struct dw_eth_dev *priv = &dev->dw;
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struct clk clk_speed;
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int ret;
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@ -159,8 +185,9 @@ static int rk1808_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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return 0;
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}
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static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
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{
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struct dw_eth_dev *priv = &dev->dw;
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struct rk322x_grf *grf;
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int clk;
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enum {
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@ -192,8 +219,9 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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return 0;
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}
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static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
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{
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struct dw_eth_dev *priv = &dev->dw;
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struct rk3288_grf *grf;
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int clk;
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@ -218,8 +246,9 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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return 0;
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}
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static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
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{
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struct dw_eth_dev *priv = &dev->dw;
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struct rk3308_grf *grf;
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struct clk clk_speed;
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int speed, ret;
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@ -259,8 +288,9 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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return 0;
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}
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static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
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{
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struct dw_eth_dev *priv = &dev->dw;
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struct rk3328_grf_regs *grf;
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int clk;
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enum {
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@ -292,8 +322,9 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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return 0;
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}
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static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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static int rk3368_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
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{
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struct dw_eth_dev *priv = &dev->dw;
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struct rk3368_grf *grf;
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int clk;
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enum {
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@ -324,8 +355,9 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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return 0;
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}
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static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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static int rk3399_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
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{
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struct dw_eth_dev *priv = &dev->dw;
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struct rk3399_grf_regs *grf;
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int clk;
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@ -350,8 +382,9 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
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return 0;
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}
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static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
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static int rv1108_set_rmii_speed(struct rockchip_eth_dev *dev)
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{
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struct dw_eth_dev *priv = &dev->dw;
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struct rv1108_grf *grf;
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int clk, speed;
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enum {
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@ -384,7 +417,9 @@ static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
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return 0;
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}
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#endif
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#ifndef CONFIG_DWC_ETH_QOS
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static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
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{
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struct px30_grf *grf;
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@ -638,18 +673,31 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
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RV1108_GMAC_PHY_INTF_SEL_MASK,
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RV1108_GMAC_PHY_INTF_SEL_RMII);
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}
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#endif
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static int gmac_rockchip_probe(struct udevice *dev)
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{
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struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
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struct rk_gmac_ops *ops =
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(struct rk_gmac_ops *)dev_get_driver_data(dev);
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struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
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struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
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#ifdef CONFIG_DWC_ETH_QOS
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struct eqos_config *config;
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#else
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struct dw_eth_pdata *dw_pdata;
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#endif
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struct eth_pdata *eth_pdata;
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struct clk clk;
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ulong rate;
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int ret;
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#ifdef CONFIG_DWC_ETH_QOS
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eth_pdata = &pdata->eth_pdata;
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config = (struct eqos_config *)&ops->config;
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eth_pdata->phy_interface = config->ops->eqos_get_interface(dev);
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#else
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dw_pdata = &pdata->dw_eth_pdata;
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eth_pdata = &dw_pdata->eth_pdata;
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#endif
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/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
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ret = clk_set_defaults(dev);
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if (ret)
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@ -700,39 +748,108 @@ static int gmac_rockchip_probe(struct udevice *dev)
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return -ENXIO;
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}
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#ifdef CONFIG_DWC_ETH_QOS
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return eqos_probe(dev);
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#else
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return designware_eth_probe(dev);
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#endif
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}
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static int gmac_rockchip_eth_write_hwaddr(struct udevice *dev)
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{
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#if defined(CONFIG_DWC_ETH_QOS)
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return eqos_write_hwaddr(dev);
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#else
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return designware_eth_write_hwaddr(dev);
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#endif
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}
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static int gmac_rockchip_eth_free_pkt(struct udevice *dev, uchar *packet,
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int length)
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{
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#ifdef CONFIG_DWC_ETH_QOS
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return eqos_free_pkt(dev, packet, length);
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#else
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return designware_eth_free_pkt(dev, packet, length);
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#endif
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}
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static int gmac_rockchip_eth_send(struct udevice *dev, void *packet,
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int length)
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{
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#ifdef CONFIG_DWC_ETH_QOS
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return eqos_send(dev, packet, length);
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#else
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return designware_eth_send(dev, packet, length);
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#endif
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}
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static int gmac_rockchip_eth_recv(struct udevice *dev, int flags,
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uchar **packetp)
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{
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#ifdef CONFIG_DWC_ETH_QOS
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return eqos_recv(dev, flags, packetp);
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#else
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return designware_eth_recv(dev, flags, packetp);
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#endif
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}
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static int gmac_rockchip_eth_start(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct dw_eth_dev *priv = dev_get_priv(dev);
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struct rockchip_eth_dev *priv = dev_get_priv(dev);
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struct rk_gmac_ops *ops =
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(struct rk_gmac_ops *)dev_get_driver_data(dev);
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#ifndef CONFIG_DWC_ETH_QOS
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struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
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struct dw_eth_pdata *dw_pdata;
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struct eth_pdata *eth_pdata;
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#endif
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int ret;
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ret = designware_eth_init(priv, pdata->enetaddr);
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#ifdef CONFIG_DWC_ETH_QOS
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ret = eqos_init(dev);
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#else
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dw_pdata = &pdata->dw_eth_pdata;
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eth_pdata = &dw_pdata->eth_pdata;
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ret = designware_eth_init((struct dw_eth_dev *)priv,
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eth_pdata->enetaddr);
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#endif
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if (ret)
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return ret;
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ret = ops->fix_mac_speed(priv);
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if (ret)
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return ret;
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ret = designware_eth_enable(priv);
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#ifdef CONFIG_DWC_ETH_QOS
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eqos_enable(dev);
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#else
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ret = designware_eth_enable((struct dw_eth_dev *)priv);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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static void gmac_rockchip_eth_stop(struct udevice *dev)
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{
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#ifdef CONFIG_DWC_ETH_QOS
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eqos_stop(dev);
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#else
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designware_eth_stop(dev);
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#endif
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}
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const struct eth_ops gmac_rockchip_eth_ops = {
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.start = gmac_rockchip_eth_start,
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.send = designware_eth_send,
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.recv = designware_eth_recv,
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.free_pkt = designware_eth_free_pkt,
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.stop = designware_eth_stop,
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.write_hwaddr = designware_eth_write_hwaddr,
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.send = gmac_rockchip_eth_send,
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.recv = gmac_rockchip_eth_recv,
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.free_pkt = gmac_rockchip_eth_free_pkt,
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.stop = gmac_rockchip_eth_stop,
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.write_hwaddr = gmac_rockchip_eth_write_hwaddr,
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};
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#ifndef CONFIG_DWC_ETH_QOS
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const struct rk_gmac_ops px30_gmac_ops = {
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.fix_mac_speed = px30_gmac_fix_mac_speed,
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.set_to_rmii = px30_gmac_set_to_rmii,
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@ -777,8 +894,10 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
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.fix_mac_speed = rv1108_set_rmii_speed,
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.set_to_rmii = rv1108_gmac_set_to_rmii,
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};
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#endif
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static const struct udevice_id rockchip_gmac_ids[] = {
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#ifndef CONFIG_DWC_ETH_QOS
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{ .compatible = "rockchip,px30-gmac",
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.data = (ulong)&px30_gmac_ops },
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{ .compatible = "rockchip,rk1808-gmac",
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@ -797,6 +916,7 @@ static const struct udevice_id rockchip_gmac_ids[] = {
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.data = (ulong)&rk3399_gmac_ops },
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{ .compatible = "rockchip,rv1108-gmac",
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.data = (ulong)&rv1108_gmac_ops },
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#endif
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{ }
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};
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@ -807,7 +927,7 @@ U_BOOT_DRIVER(eth_gmac_rockchip) = {
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.ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
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.probe = gmac_rockchip_probe,
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.ops = &gmac_rockchip_eth_ops,
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.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
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.priv_auto_alloc_size = sizeof(struct rockchip_eth_dev),
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.platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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