Merge branch 'next-dev' into thunder-boot

common/spl/spl_rkfw.c

@@ -7,6 +7,7 @@
 #include <android_image.h>
 #include <errno.h>
 #include <malloc.h>
+#include <misc.h>
 #include <misc_decompress.h>
 #include <spl.h>
 #include <spl_rkfw.h>
@@ -343,7 +344,7 @@ static int rkfw_load_kernel(struct spl_load_info *info, u32 image_sector,
 	}
 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS
 	struct udevice *dev;
-	u32 cap = GZIP_MOD;
+	u32 cap = DECOM_GZIP;
 
 	dev = misc_decompress_get_device(cap);
 

drivers/misc/Kconfig

@@ -86,6 +86,12 @@ config SPL_ROCKCHIP_SECURE_OTP
 	help
 	  Support read & write secure otp in spl.
 
+config SPL_ROCKCHIP_SECURE_OTP_V2
+	bool "Rockchip Secure OTP Version 2 Support in spl"
+	depends on SPL_MISC
+	help
+	  Support read & write secure otp in spl. Support platforms: rv1126.
+
 config CMD_CROS_EC
 	bool "Enable crosec command"
 	depends on CROS_EC

drivers/misc/Makefile

@@ -54,5 +54,6 @@ obj-$(CONFIG_QFW) += qfw.o
 obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
 obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
 obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP) += rockchip-secure-otp.o
+obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP_V2) += rockchip-secure-otp-v2.o
 obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_HW_DECOMPRESS) += rockchip_decompress.o
-obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_HW_DECOMPRESS) += misc_decompress.o
+obj-$(CONFIG_$(SPL_TPL_)MISC) += misc_decompress.o misc_otp.o

drivers/misc/misc_decompress.c

@@ -79,7 +79,7 @@ int misc_decompress_start(struct udevice *dev, unsigned long src,
 	param.addr_src = src;
 	param.size = size;
 	if (misc_gzip_parse_header((unsigned char *)src, 0xffff) > 0) {
-		param.mode = GZIP_MOD;
+		param.mode = DECOM_GZIP;
 	} else {
 		printf("Unsupported decompression format.\n");
 		return -EPERM;

drivers/misc/misc_otp.c

@@ -0,0 +1,46 @@
+// SPDX-License-Identifier:     GPL-2.0+
+/*
+ * Copyright (C) 2020 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <misc.h>
+
+struct udevice *misc_otp_get_device(u32 capability)
+{
+	const struct misc_ops *ops;
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
+	u32 cap;
+
+	ret = uclass_get(UCLASS_MISC, &uc);
+	if (ret)
+		return NULL;
+
+	for (uclass_first_device(UCLASS_MISC, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		ops = device_get_ops(dev);
+		if (!ops || !ops->ioctl)
+			continue;
+
+		cap = ops->ioctl(dev, IOCTL_REQ_CAPABILITY, NULL);
+		if ((cap & capability) == capability)
+			return dev;
+	}
+
+	return NULL;
+}
+
+int misc_otp_read(struct udevice *dev, int offset, void *buf, int size)
+{
+	return misc_read(dev, offset, buf, size);
+}
+
+int misc_otp_write(struct udevice *dev, int offset, const void *buf, int size)
+{
+	return misc_write(dev, offset, (void *)buf, size);
+}

drivers/misc/rockchip_decompress.c

@@ -63,6 +63,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DECOM_GZIP_MODE		BIT(4)
 #define DECOM_ZLIB_MODE		BIT(5)
 #define DECOM_DEFLATE_MODE	BIT(0)
+#define DECOM_LZ4_MODE		0
 
 #define DECOM_ENABLE		0x1
 #define DECOM_DISABLE		0x0
@@ -92,17 +93,17 @@ static int rockchip_decom_start(struct udevice *dev, void *buf)
 	writel(0x00800080, priv->soft_reset_base);
 	writel(0x00800000, priv->soft_reset_base);
 
-	if (param->mode == LZ4_MOD)
+	if (param->mode == DECOM_LZ4)
 		writel(LZ4_CONT_CSUM_CHECK_EN |
 		       LZ4_HEAD_CSUM_CHECK_EN |
 		       LZ4_BLOCK_CSUM_CHECK_EN |
-		       LZ4_MOD, priv->base + DECOM_CTRL);
+		       DECOM_LZ4_MODE, priv->base + DECOM_CTRL);
 
-	if (param->mode == GZIP_MOD)
+	if (param->mode == DECOM_GZIP)
 		writel(DECOM_DEFLATE_MODE | DECOM_GZIP_MODE,
 		       priv->base + DECOM_CTRL);
 
-	if (param->mode == ZLIB_MOD)
+	if (param->mode == DECOM_ZLIB)
 		writel(DECOM_DEFLATE_MODE | DECOM_ZLIB_MODE,
 		       priv->base + DECOM_CTRL);
 
@@ -145,7 +146,7 @@ static int rockchip_decom_done_poll(struct udevice *dev)
 
 static int rockchip_decom_ability(void)
 {
-	return GZIP_MOD;
+	return DECOM_GZIP;
 }
 
 /* Caller must fill in param @buf which represent struct decom_param */

drivers/mtd/nand/raw/rockchip_nand_spl.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <fdtdec.h>
 #include <fdt_support.h>
 #include <inttypes.h>
@@ -80,6 +81,8 @@ struct rk_nand {
 	u8 chipnr;
 	u8 id[5];
 	u8 *databuf;
+	struct udevice *dev;
+	struct mtd_info *mtd;
 };
 
 struct rk_nand *g_rk_nand;
@@ -248,10 +251,175 @@ static void read_flash_id(struct rk_nand *rknand, uint8_t *id)
 	id[3] = readb(bank_base);
 	id[4] = readb(bank_base);
 	rockchip_nand_select_chip(rknand->regs, -1);
-	printf("%s %x %x %x %x %x\n", __func__, id[0], id[1], id[2], id[3],
+	if (id[0] != 0xFF && id[0] != 0x00)
-	       id[4]);
+		printf("NAND:%x %x\n", id[0], id[1]);
 }
 
+#ifdef CONFIG_NAND_ROCKCHIP_DT
+static const struct udevice_id rockchip_nandc_ids[] = {
+	{ .compatible = "rockchip,rk-nandc" },
+	{ }
+};
+
+static int spl_nand_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+	return is_badblock(ofs / CONFIG_SYS_NAND_PAGE_SIZE);
+}
+
+static int spl_nand_read_page(struct mtd_info *mtd, loff_t from, size_t len,
+			      size_t *retlen, u_char *buf)
+{
+	int read_size, offset, read_len;
+	unsigned int page;
+	unsigned int max_pages = CONFIG_SYS_NAND_SIZE /
+				CONFIG_SYS_NAND_PAGE_SIZE;
+
+	/* Convert to page number */
+	page = from / CONFIG_SYS_NAND_PAGE_SIZE;
+	offset = from & (CONFIG_SYS_NAND_PAGE_SIZE - 1);
+	read_len = len;
+	*retlen = 0;
+
+	while (read_len) {
+		read_size = CONFIG_SYS_NAND_PAGE_SIZE - offset;
+		if (read_size > read_len)
+			read_size = read_len;
+		if (offset || read_size < CONFIG_SYS_NAND_PAGE_SIZE) {
+			if (nandc_read_page(page, g_rk_nand->databuf) < 0)
+				return -EIO;
+			memcpy(buf, g_rk_nand->databuf + offset, read_size);
+			offset = 0;
+		} else {
+			if (nandc_read_page(page, buf) < 0)
+				return -EIO;
+		}
+		page++;
+		read_len -= read_size;
+		buf += read_size;
+		if (page >= max_pages)
+			return -EIO;
+	}
+
+	*retlen = len;
+
+	return 0;
+}
+
+static int rockchip_nandc_probe(struct udevice *dev)
+{
+	const void *blob = gd->fdt_blob;
+	struct rk_nand *rknand = dev_get_priv(dev);
+	struct mtd_info *mtd = dev_get_uclass_priv(dev);
+	fdt_addr_t regs;
+	int ret = -ENODEV;
+	int node;
+
+	g_rk_nand = rknand;
+	rknand->dev = dev;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC);
+
+	if (node < 0) {
+		printf("Nand node not found\n");
+		return -ENODEV;
+	}
+
+	if (!fdtdec_get_is_enabled(blob, node)) {
+		debug("Nand disabled in device tree\n");
+		return -ENODEV;
+	}
+
+	regs = fdt_get_base_address(blob, node);
+	if (!regs) {
+		debug("Nand address not found\n");
+		return -ENODEV;
+	}
+
+	rknand->regs = (void *)regs;
+
+	nandc_init(g_rk_nand);
+	read_flash_id(g_rk_nand, g_rk_nand->id);
+
+	if (g_rk_nand->id[0] == g_rk_nand->id[1])
+		return -ENODEV;
+
+	if (g_rk_nand->id[1] == 0xA1 || g_rk_nand->id[1] == 0xF1 ||
+	    g_rk_nand->id[1] == 0xD1 || g_rk_nand->id[1] == 0xAA ||
+	    g_rk_nand->id[1] == 0xDA || g_rk_nand->id[1] == 0xAC ||
+	    g_rk_nand->id[1] == 0xDC || g_rk_nand->id[1] == 0xA3 ||
+	    g_rk_nand->id[1] == 0xD3 || g_rk_nand->id[1] == 0x95 ||
+	    g_rk_nand->id[1] == 0x48) {
+		g_rk_nand->chipnr = 1;
+		g_rk_nand->databuf = kzalloc(CONFIG_SYS_NAND_PAGE_SIZE,
+					     GFP_KERNEL);
+		if (!g_rk_nand)
+			return -ENOMEM;
+		mtd->_block_isbad = spl_nand_block_isbad;
+		mtd->_read = spl_nand_read_page;
+		mtd->size = CONFIG_SYS_NAND_SIZE;
+		mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+		mtd->type = MTD_NANDFLASH;
+		mtd->dev = rknand->dev;
+		mtd->priv = rknand;
+		add_mtd_device(mtd);
+		mtd->name = "rk-nand";
+		rknand->mtd = mtd;
+		ret = 0;
+	}
+
+	return ret;
+}
+
+static int rockchip_nandc_bind(struct udevice *udev)
+{
+	int ret = 0;
+
+#ifdef CONFIG_MTD_BLK
+	struct udevice *bdev;
+
+	ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD,
+				 BLK_MTD_NAND, 512, 0, &bdev);
+	if (ret)
+		printf("Cannot create block device\n");
+#endif
+	return ret;
+}
+
+U_BOOT_DRIVER(rk_nandc_v6) = {
+	.name           = "rk_nandc_v6",
+	.id             = UCLASS_MTD,
+	.of_match       = rockchip_nandc_ids,
+	.bind		= rockchip_nandc_bind,
+	.probe          = rockchip_nandc_probe,
+	.priv_auto_alloc_size = sizeof(struct rk_nand),
+};
+
+void board_nand_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_GET_DRIVER(rk_nandc_v6),
+					  &dev);
+	if (ret && ret != -ENODEV)
+		pr_err("Failed to initialize NAND controller. (error %d)\n",
+		       ret);
+}
+
+int nand_spl_load_image(u32 offs, u32 size, void *buf)
+{
+	return -EIO;
+}
+
+void nand_init(void){};
+
+int rk_nand_init(void)
+{
+	return -ENODEV;
+}
+
+#else
 void board_nand_init(void)
 {
 	const void *blob = gd->fdt_blob;
@@ -271,18 +439,18 @@ void board_nand_init(void)
 
 	if (node < 0) {
 		printf("Nand node not found\n");
-		goto err;
+		return;
 	}
 
 	if (!fdtdec_get_is_enabled(blob, node)) {
 		debug("Nand disabled in device tree\n");
-		goto err;
+		return;
 	}
 
 	regs = fdt_get_base_address(blob, node);
-	if (regs == FDT_ADDR_T_NONE) {
+	if (!regs) {
 		debug("Nand address not found\n");
-		goto err;
+		return;
 	}
 
 	g_rk_nand = kzalloc(sizeof(*g_rk_nand), GFP_KERNEL);
@@ -290,12 +458,24 @@ void board_nand_init(void)
 	g_rk_nand->databuf = kzalloc(CONFIG_SYS_NAND_PAGE_SIZE, GFP_KERNEL);
 	nandc_init(g_rk_nand);
 	read_flash_id(g_rk_nand, g_rk_nand->id);
-	if (g_rk_nand->id[0] != 0xFF && g_rk_nand->id[1] != 0xFF &&
+
-	    g_rk_nand->id[0] != 0x00 && g_rk_nand->id[1] != 0x00)
+	if (g_rk_nand->id[0] == g_rk_nand->id[1])
+		goto err;
+
+	if (g_rk_nand->id[1] == 0xA1 || g_rk_nand->id[1] == 0xF1 ||
+	    g_rk_nand->id[1] == 0xD1 || g_rk_nand->id[1] == 0xAA ||
+	    g_rk_nand->id[1] == 0xDA || g_rk_nand->id[1] == 0xAC ||
+	    g_rk_nand->id[1] == 0xDC || g_rk_nand->id[1] == 0xA3 ||
+	    g_rk_nand->id[1] == 0xD3 || g_rk_nand->id[1] == 0x95 ||
+	    g_rk_nand->id[1] == 0x48) {
 		g_rk_nand->chipnr = 1;
-	return;
+		return;
+	}
+
 err:
+	kfree(g_rk_nand->databuf);
 	kfree(g_rk_nand);
+	g_rk_nand = NULL;
 }
 
 int nand_spl_load_image(u32 offs, u32 size, void *buf)
@@ -351,5 +531,7 @@ int rk_nand_init(void)
 	else
 		return -ENODEV;
 }
+#endif
 
 void nand_deselect(void) {}
+

drivers/sysreset/Makefile

@@ -8,9 +8,6 @@ obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_SYSRESET) += sysreset-syscon-reboot.o
-endif
-
-ifndef CONFIG_TPL_BUILD
 obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
 endif
 

drivers/sysreset/sysreset-uclass.c

@@ -34,7 +34,7 @@ int sysreset_walk(enum sysreset_t type)
 	 * Use psci sysreset as primary for rockchip platforms,
 	 * "rockchip_reset" is applied if PSCI is disabled.
 	 */
-#if !defined(CONFIG_TPL_BUILD) && \
+#if !defined(CONFIG_SPL_BUILD) && \
      defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_SYSRESET_PSCI)
 	ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
 					  DM_GET_DRIVER(psci_sysreset), &dev);

include/misc.h

@@ -17,6 +17,14 @@
 #define IOCTL_REQ_POLL		_IO('m', 0x03)
 #define IOCTL_REQ_CAPABILITY	_IO('m', 0x04)
 
+enum misc_mode {
+	DECOM_LZ4	= BIT(0),
+	DECOM_GZIP	= BIT(1),
+	DECOM_ZLIB	= BIT(2),
+	OTP_S		= BIT(3),
+	OTP_NS		= BIT(4),
+};
+
 /*
  * Read the device to buffer, optional.
  *

include/misc_decompress.h

@@ -6,17 +6,11 @@
 #ifndef _MISC_DECOMPRESS_H_
 #define _MISC_DECOMPRESS_H_
 
-enum decom_mod {
-	LZ4_MOD,
-	GZIP_MOD,
-	ZLIB_MOD,
-};
-
 struct decom_param {
 	unsigned long addr_src;
 	unsigned long addr_dst;
 	unsigned long size;
-	enum decom_mod mode;
+	enum misc_mode mode;
 };
 
 struct udevice *misc_decompress_get_device(u32 capability);

include/misc_otp.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __MISC_OTP_H__
+#define __MISC_OTP_H__
+
+struct udevice *misc_otp_get_device(u32 capability);
+int misc_otp_read(struct udevice *dev, int offset, void *buf, int size);
+int misc_otp_write(struct udevice *dev, int offset, const void *buf, int size);
+
+#endif

include/rockchip-otp-v2.h

@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ROCKCHIP_OTP_V2_H_
+#define _ROCKCHIP_OTP_V2_H_
+
+#define NVM_CEB			0x00
+#define NVM_RSTB		0x04
+#define NVM_TCSRST		0x08
+#define NVM_TCEW		0x0c
+#define NVM_TRW			0x10
+#define NVM_TRS			0x14
+#define NVM_ST			0x18
+#define NVM_RADDR		0x1c
+#define NVM_RSTART		0x20
+#define NVM_RDATA		0x24
+#define NVM_TRWH		0x28
+#define NVM_TREW		0x2c
+#define NVM_READ_ST		0x30
+#define NVM_PRADDR		0x34
+#define NVM_PRLEN		0x38
+#define NVM_PRDATA		0x3c
+#define NVM_FAILTIME		0x40
+#define NVM_PRSTART		0x44
+#define NVM_PRSTATE		0x48
+#define NVM_PRSUCCESS		0x4c
+#define NVM_TAS			0x50
+#define NVM_TWWL		0x54
+#define NVM_TDLEH		0x58
+#define NVM_TDPD		0x5c
+#define NVM_TPES		0x60
+#define NVM_TCPS		0x64
+#define NVM_TPW			0x68
+#define NVM_TCPH		0x6c
+#define NVM_TPEH		0x70
+#define NVM_TPTPD		0x74
+#define NVM_TPGMAS		0x78
+#define OTPC_INT_ST		0x7c
+#define NVM_INT_EN		0x80
+#define OTP_PROG_MASK_BASE	0x0200
+#define OTP_READ_MASK_BASE	0x0300
+#define OTP_MASK_BYPASS		0x0400
+#define OTP_MASK_INT_CON	0x0404
+#define OTP_MASK_INT_STATUS	0x0408
+#define OTP_MASK_STATUS		0x040C
+#define OTP_MASK_PROG_LOCK	0x0410
+#define OTP_MASK_READ_LOCK	0x0414
+#define OTP_MASK_BYPASS_LOCK	0x0418
+#define OTP_SLICE_LOCK		0x041c
+#define OTP_SLICE		0x0420
+
+struct rockchip_otp_v2_platdata {
+	void __iomem *base;
+	unsigned long secure_conf_base;
+};
+
+#endif
+