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rockchip: dts: rk3328: add rk3328-u-boot.dtsi 

Change-Id: I0fa2256aa02452b4e56fb7b2c035025e49cf61a8
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This commit is contained in:
Joseph Chen 2018-07-16 14:58:50 +08:00
parent 669ef96c7a
commit 766c66006c
3 changed files with 37 additions and 5 deletions
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3
arch/arm/dts/rk3328-evb.dts
View File

@ -6,6 +6,7 @@
/dts-v1/; /dts-v1/;
#include "rk3328.dtsi" #include "rk3328.dtsi"
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr3-666.dtsi" #include "rk3328-sdram-ddr3-666.dtsi"
/ { / {
@ -62,7 +63,6 @@
}; };
&uart2 { &uart2 {
u-boot,dm-pre-reloc;
status = "okay"; status = "okay";
}; };
@ -79,7 +79,6 @@
}; };
&emmc { &emmc {
u-boot,dm-pre-reloc;
bus-width = <8>; bus-width = <8>;
cap-mmc-highspeed; cap-mmc-highspeed;
supports-emmc; supports-emmc;

36
arch/arm/dts/rk3328-u-boot.dtsi Normal file
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@ -0,0 +1,36 @@
/*
* (C) Copyright 2018 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
};
&cru {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&dmc {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};

3
arch/arm/dts/rk3328.dtsi
View File

@ -187,7 +187,6 @@
}; };
grf: syscon@ff100000 { grf: syscon@ff100000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>; reg = <0x0 0xff100000 0x0 0x1000>;
#address-cells = <1>; #address-cells = <1>;
@ -355,7 +354,6 @@
}; };
dmc: dmc { dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-dmc"; compatible = "rockchip,rk3328-dmc";
reg = <0x0 0xff400000 0x0 0x1000 reg = <0x0 0xff400000 0x0 0x1000
0x0 0xff780000 0x0 0x3000 0x0 0xff780000 0x0 0x3000
@ -366,7 +364,6 @@
}; };
cru: clock-controller@ff440000 { cru: clock-controller@ff440000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>; reg = <0x0 0xff440000 0x0 0x1000>;
rockchip,grf = <&grf>; rockchip,grf = <&grf>;