rockchip: add rk3568 SoC support
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I2e163b93d4ec5a60f1ff9c589626d3ccd994f854
This commit is contained in:
Joseph Chen
Jianhong Chen
parent
be7064f8f7
commit
7e26af3867
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@ -0,0 +1,399 @@
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/*
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* (C) Copyright 2020 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_GRF_RK3568_H
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#define _ASM_ARCH_GRF_RK3568_H
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#include <common.h>
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struct rk3568_grf {
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unsigned int gpio1a_iomux_l;
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unsigned int gpio1a_iomux_h;
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unsigned int gpio1b_iomux_l;
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unsigned int gpio1b_iomux_h;
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unsigned int gpio1c_iomux_l;
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unsigned int gpio1c_iomux_h;
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unsigned int gpio1d_iomux_l;
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unsigned int gpio1d_iomux_h;
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unsigned int gpio2a_iomux_l;
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unsigned int gpio2a_iomux_h;
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unsigned int gpio2b_iomux_l;
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unsigned int gpio2b_iomux_h;
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unsigned int gpio2c_iomux_l;
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unsigned int gpio2c_iomux_h;
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unsigned int gpio2d_iomux_l;
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unsigned int gpio2d_iomux_h;
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unsigned int gpio3a_iomux_l;
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unsigned int gpio3a_iomux_h;
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unsigned int gpio3b_iomux_l;
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unsigned int gpio3b_iomux_h;
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unsigned int gpio3c_iomux_l;
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unsigned int gpio3c_iomux_h;
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unsigned int gpio3d_iomux_l;
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unsigned int gpio3d_iomux_h;
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unsigned int gpio4a_iomux_l;
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unsigned int gpio4a_iomux_h;
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unsigned int gpio4b_iomux_l;
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unsigned int gpio4b_iomux_h;
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unsigned int gpio4c_iomux_l;
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unsigned int gpio4c_iomux_h;
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unsigned int gpio4d_iomux_l;
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unsigned int reserved0[(0x0080 - 0x0078) / 4 - 1];
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unsigned int gpio1a_p;
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unsigned int gpio1b_p;
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unsigned int gpio1c_p;
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unsigned int gpio1d_p;
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unsigned int gpio2a_p;
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unsigned int gpio2b_p;
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unsigned int gpio2c_p;
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unsigned int gpio2d_p;
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unsigned int gpio3a_p;
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unsigned int gpio3b_p;
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unsigned int gpio3c_p;
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unsigned int gpio3d_p;
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unsigned int gpio4a_p;
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unsigned int gpio4b_p;
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unsigned int gpio4c_p;
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unsigned int gpio4d_p;
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unsigned int gpio1a_ie;
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unsigned int gpio1b_ie;
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unsigned int gpio1c_ie;
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unsigned int gpio1d_ie;
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unsigned int gpio2a_ie;
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unsigned int gpio2b_ie;
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unsigned int gpio2c_ie;
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unsigned int gpio2d_ie;
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unsigned int gpio3a_ie;
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unsigned int gpio3b_ie;
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unsigned int gpio3c_ie;
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unsigned int gpio3d_ie;
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unsigned int gpio4a_ie;
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unsigned int gpio4b_ie;
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unsigned int gpio4c_ie;
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unsigned int gpio4d_ie;
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unsigned int gpio1a_opd;
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unsigned int gpio1b_opd;
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unsigned int gpio1c_opd;
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unsigned int gpio1d_opd;
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unsigned int gpio2a_opd;
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unsigned int gpio2b_opd;
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unsigned int gpio2c_opd;
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unsigned int gpio2d_opd;
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unsigned int gpio3a_opd;
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unsigned int gpio3b_opd;
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unsigned int gpio3c_opd;
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unsigned int gpio3d_opd;
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unsigned int gpio4a_opd;
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unsigned int gpio4b_opd;
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unsigned int gpio4c_opd;
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unsigned int gpio4d_opd;
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unsigned int gpio1a_sus;
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unsigned int gpio1b_sus;
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unsigned int gpio1c_sus;
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unsigned int gpio1d_sus;
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unsigned int gpio2a_sus;
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unsigned int gpio2b_sus;
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unsigned int gpio2c_sus;
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unsigned int gpio2d_sus;
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unsigned int gpio3a_sus;
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unsigned int gpio3b_sus;
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unsigned int gpio3c_sus;
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unsigned int gpio3d_sus;
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unsigned int gpio4a_sus;
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unsigned int gpio4b_sus;
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unsigned int gpio4c_sus;
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unsigned int gpio4d_sus;
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unsigned int gpio1a_sl;
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unsigned int gpio1b_sl;
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unsigned int gpio1c_sl;
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unsigned int gpio1d_sl;
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unsigned int gpio2a_sl;
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unsigned int gpio2b_sl;
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unsigned int gpio2c_sl;
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unsigned int gpio2d_sl;
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unsigned int gpio3a_sl;
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unsigned int gpio3b_sl;
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unsigned int gpio3c_sl;
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unsigned int gpio3d_sl;
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unsigned int gpio4a_sl;
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unsigned int gpio4b_sl;
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unsigned int gpio4c_sl;
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unsigned int gpio4d_sl;
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unsigned int reserved1[(0x0200 - 0x01bc) / 4 - 1];
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unsigned int gpio1a_ds_0;
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unsigned int gpio1a_ds_1;
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unsigned int gpio1a_ds_2;
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unsigned int gpio1a_ds_3;
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unsigned int gpio1b_ds_0;
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unsigned int gpio1b_ds_1;
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unsigned int gpio1b_ds_2;
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unsigned int gpio1b_ds_3;
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unsigned int gpio1c_ds_0;
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unsigned int gpio1c_ds_1;
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unsigned int gpio1c_ds_2;
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unsigned int gpio1c_ds_3;
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unsigned int gpio1d_ds_0;
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unsigned int gpio1d_ds_1;
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unsigned int gpio1d_ds_2;
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unsigned int gpio1d_ds_3;
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unsigned int gpio2a_ds_0;
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unsigned int gpio2a_ds_1;
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unsigned int gpio2a_ds_2;
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unsigned int gpio2a_ds_3;
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unsigned int gpio2b_ds_0;
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unsigned int gpio2b_ds_1;
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unsigned int gpio2b_ds_2;
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unsigned int gpio2b_ds_3;
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unsigned int gpio2c_ds_0;
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unsigned int gpio2c_ds_1;
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unsigned int gpio2c_ds_2;
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unsigned int gpio2c_ds_3;
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unsigned int gpio2d_ds_0;
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unsigned int gpio2d_ds_1;
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unsigned int gpio2d_ds_2;
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unsigned int gpio2d_ds_3;
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unsigned int gpio3a_ds_0;
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unsigned int gpio3a_ds_1;
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unsigned int gpio3a_ds_2;
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unsigned int gpio3a_ds_3;
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unsigned int gpio3b_ds_0;
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unsigned int gpio3b_ds_1;
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unsigned int gpio3b_ds_2;
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unsigned int gpio3b_ds_3;
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unsigned int gpio3c_ds_0;
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unsigned int gpio3c_ds_1;
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unsigned int gpio3c_ds_2;
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unsigned int gpio3c_ds_3;
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unsigned int gpio3d_ds_0;
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unsigned int gpio3d_ds_1;
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unsigned int gpio3d_ds_2;
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unsigned int gpio3d_ds_3;
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unsigned int gpio4a_ds_0;
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unsigned int gpio4a_ds_1;
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unsigned int gpio4a_ds_2;
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unsigned int gpio4a_ds_3;
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unsigned int gpio4b_ds_0;
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unsigned int gpio4b_ds_1;
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unsigned int gpio4b_ds_2;
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unsigned int gpio4b_ds_3;
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unsigned int gpio4c_ds_0;
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unsigned int gpio4c_ds_1;
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unsigned int gpio4c_ds_2;
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unsigned int gpio4c_ds_3;
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unsigned int gpio4d_ds_0;
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unsigned int gpio4d_ds_1;
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unsigned int gpio4d_ds_2;
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unsigned int gpio4d_ds_3;
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unsigned int iofunc_sel0;
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unsigned int iofunc_sel1;
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unsigned int iofunc_sel2;
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unsigned int iofunc_sel3;
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unsigned int iofunc_sel4;
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unsigned int iofunc_sel5;
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unsigned int reserved2[(0x0340 - 0x0314) / 4 - 1];
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unsigned int vi_con0;
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unsigned int vi_con1;
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unsigned int vi_status0;
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unsigned int reserved3[(0x0360 - 0x0348) / 4 - 1];
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unsigned int vo_con0;
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unsigned int vo_con1;
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unsigned int vo_con2;
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unsigned int vo_con3;
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unsigned int reserved4[(0x0380 - 0x036c) / 4 - 1];
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unsigned int mac0_con0;
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unsigned int mac0_con1;
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unsigned int mac1_con0;
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unsigned int mac1_con1;
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unsigned int reserved5[(0x03a0 - 0x038c) / 4 - 1];
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unsigned int biu_con0;
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unsigned int biu_con1;
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unsigned int biu_con2;
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unsigned int reserved6[(0x03c0 - 0x03a8) / 4 - 1];
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unsigned int gic_con0;
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unsigned int gic_con1;
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unsigned int gic_con2;
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unsigned int reserved7[(0x03f0 - 0x03c8) / 4 - 1];
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unsigned int gpu_con0;
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unsigned int gpu_con1;
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unsigned int reserved8[(0x0400 - 0x03f4) / 4 - 1];
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unsigned int cpu_con0;
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unsigned int reserved9[(0x0420 - 0x0400) / 4 - 1];
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unsigned int cpu_status0;
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unsigned int reserved10[(0x0500 - 0x0420) / 4 - 1];
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unsigned int soc_con0;
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unsigned int soc_con1;
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unsigned int soc_con2;
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unsigned int soc_con3;
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unsigned int reserved11[(0x0514 - 0x050c) / 4 - 1];
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unsigned int soc_con5;
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unsigned int soc_con6;
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unsigned int reserved12[(0x0580 - 0x0518) / 4 - 1];
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unsigned int soc_status0;
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unsigned int reserved13[(0x05c0 - 0x0580) / 4 - 1];
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unsigned int ram_con;
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unsigned int core_ram_con;
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unsigned int reserved14[(0x0600 - 0x05c4) / 4 - 1];
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unsigned int tsadc_con;
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unsigned int reserved15[(0x0610 - 0x0600) / 4 - 1];
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unsigned int saradc_con;
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unsigned int reserved16[(0x0700 - 0x0610) / 4 - 1];
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unsigned int gpupvtpll_con0;
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unsigned int gpupvtpll_con1;
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unsigned int gpupvtpll_con2;
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unsigned int gpupvtpll_con3;
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unsigned int reserved17[(0x0740 - 0x070c) / 4 - 1];
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unsigned int npupvtpll_con0;
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unsigned int npupvtpll_con1;
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unsigned int npupvtpll_con2;
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unsigned int npupvtpll_con3;
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unsigned int reserved18[(0x0800 - 0x074c) / 4 - 1];
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unsigned int chip_id;
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unsigned int reserved19[(0x0840 - 0x0800) / 4 - 1];
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unsigned int gpio1c5_ds;
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unsigned int gpio2a2_ds;
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unsigned int gpio2b0_ds;
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unsigned int gpio3a0_ds;
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unsigned int gpio3a6_ds;
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unsigned int gpio4a0_ds;
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unsigned int reserved20[(0x0900 - 0x0854) / 4 - 1];
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unsigned int dmac0_con0;
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unsigned int dmac0_con1;
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unsigned int dmac0_con2;
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unsigned int dmac0_con3;
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unsigned int dmac0_con4;
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unsigned int dmac0_con5;
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unsigned int dmac0_con6;
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unsigned int dmac0_con7;
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unsigned int dmac0_con8;
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unsigned int dmac0_con9;
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unsigned int reserved21[(0x0940 - 0x0924) / 4 - 1];
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unsigned int dmac1_con0;
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unsigned int dmac1_con1;
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unsigned int dmac1_con2;
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unsigned int dmac1_con3;
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unsigned int dmac1_con4;
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unsigned int dmac1_con5;
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unsigned int dmac1_con6;
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unsigned int dmac1_con7;
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unsigned int dmac1_con8;
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unsigned int dmac1_con9;
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};
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check_member(rk3568_grf, dmac1_con9, 0x0964);
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struct rk3568_pmugrf {
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unsigned int pmu_gpio0a_iomux_l;
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unsigned int pmu_gpio0a_iomux_h;
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unsigned int pmu_gpio0b_iomux_l;
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unsigned int pmu_gpio0b_iomux_h;
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unsigned int pmu_gpio0c_iomux_l;
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unsigned int pmu_gpio0c_iomux_h;
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unsigned int pmu_gpio0d_iomux_l;
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unsigned int reserved0[(0x0020 - 0x0018) / 4 - 1];
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unsigned int pmu_gpio0a_p;
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unsigned int pmu_gpio0b_p;
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unsigned int pmu_gpio0c_p;
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unsigned int pmu_gpio0d_p;
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unsigned int pmu_gpio0a_ie;
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unsigned int pmu_gpio0b_ie;
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unsigned int pmu_gpio0c_ie;
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unsigned int pmu_gpio0d_ie;
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unsigned int pmu_gpio0a_opd;
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unsigned int pmu_gpio0b_opd;
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unsigned int pmu_gpio0c_opd;
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unsigned int pmu_gpio0d_opd;
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unsigned int pmu_gpio0a_sus;
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unsigned int pmu_gpio0b_sus;
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unsigned int pmu_gpio0c_sus;
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unsigned int pmu_gpio0d_sus;
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unsigned int pmu_gpio0a_sl;
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unsigned int pmu_gpio0b_sl;
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unsigned int pmu_gpio0c_sl;
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unsigned int pmu_gpio0d_sl;
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unsigned int pmu_gpio0a_ds_0;
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unsigned int pmu_gpio0a_ds_1;
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unsigned int pmu_gpio0a_ds_2;
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unsigned int pmu_gpio0a_ds_3;
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unsigned int pmu_gpio0b_ds_0;
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unsigned int pmu_gpio0b_ds_1;
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unsigned int pmu_gpio0b_ds_2;
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unsigned int pmu_gpio0b_ds_3;
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unsigned int pmu_gpio0c_ds_0;
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unsigned int pmu_gpio0c_ds_1;
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unsigned int pmu_gpio0c_ds_2;
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unsigned int pmu_gpio0c_ds_3;
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unsigned int pmu_gpio0d_ds_0;
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unsigned int pmu_gpio0d_ds_1;
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unsigned int pmu_gpio0d_ds_2;
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unsigned int pmu_gpio0d_ds_3;
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unsigned int reserved1[(0x0100 - 0x00ac) / 4 - 1];
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unsigned int pmu_soc_con0;
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unsigned int pmu_soc_con1;
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unsigned int pmu_soc_con2;
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unsigned int pmu_soc_con3;
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unsigned int pmu_soc_con4;
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unsigned int pmu_soc_con5;
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unsigned int reserved2[(0x0124 - 0x0114) / 4 - 1];
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unsigned int pmu_io_vsel0;
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unsigned int pmu_io_vsel1;
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unsigned int pmu_io_vsel2;
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unsigned int reserved3[(0x0180 - 0x012c) / 4 - 1];
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unsigned int pmu_dll_con0;
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unsigned int reserved4[(0x0200 - 0x0180) / 4 - 1];
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unsigned int pmu_os_reg0;
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unsigned int pmu_os_reg1;
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unsigned int pmu_os_reg2;
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unsigned int pmu_os_reg3;
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unsigned int pmu_os_reg4;
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unsigned int pmu_os_reg5;
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unsigned int pmu_os_reg6;
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unsigned int pmu_os_reg7;
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unsigned int pmu_os_reg8;
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unsigned int pmu_os_reg9;
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unsigned int pmu_os_reg10;
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unsigned int pmu_os_reg11;
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unsigned int pmu_reset_function_status;
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unsigned int pmu_reset_function_clr;
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unsigned int reserved5[(0x0380 - 0x0234) / 4 - 1];
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unsigned int pmu_sig_detect_con;
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unsigned int reserved6[(0x0390 - 0x0380) / 4 - 1];
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unsigned int pmu_sig_detect_status;
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unsigned int reserved7[(0x03a0 - 0x0390) / 4 - 1];
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unsigned int pmu_sig_detect_status_clear;
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unsigned int reserved8[(0x03b0 - 0x03a0) / 4 - 1];
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unsigned int pmu_sdmmc_det_counter;
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};
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check_member(rk3568_pmugrf, pmu_sdmmc_det_counter, 0x03b0);
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struct rk3568_ddrgrf {
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unsigned int ddr_con0;
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unsigned int ddr_con1;
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unsigned int ddr_con2;
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unsigned int ddr_con3;
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unsigned int ddr_con4;
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unsigned int ddr_split_con;
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unsigned int reserved0[(0x0020 - 0x0014) / 4 - 1];
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unsigned int ddr_lp_con;
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unsigned int reserved1[(0x0100 - 0x0020) / 4 - 1];
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unsigned int ddr_status0;
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unsigned int ddr_status1;
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unsigned int ddr_status2;
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unsigned int ddr_status3;
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unsigned int ddr_status4;
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unsigned int ddr_status5;
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unsigned int ddr_status6;
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unsigned int ddr_status7;
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unsigned int ddr_status8;
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unsigned int ddr_status9;
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unsigned int reserved2[(0x0130 - 0x0124) / 4 - 1];
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unsigned int ddr_status10;
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unsigned int ddr_status11;
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unsigned int ddr_status12;
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};
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check_member(rk3568_ddrgrf, ddr_status12, 0x0138);
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#endif
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@ -365,6 +365,21 @@ config TPL_STACK
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endif
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config ROCKCHIP_RK3568
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bool "Support Rockchip RK3568"
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select ARM64
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select SPL
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select SUPPORT_SPL
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help
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The Rockchip RK3568 is a ARM-based SoC with a quad-core Cortex-A55.
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if ROCKCHIP_RK3568
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|
||||
config TPL_LDSCRIPT
|
||||
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
|
||||
|
||||
endif
|
||||
|
||||
config ROCKCHIP_RK1808
|
||||
bool "Support Rockchip RK1808"
|
||||
select ARM64
|
||||
|
|
@ -489,6 +504,7 @@ config ROCKCHIP_BOOT_MODE_REG
|
|||
default 0xff1005c8 if ROCKCHIP_RK3328
|
||||
default 0xff738200 if ROCKCHIP_RK3368
|
||||
default 0xff320300 if ROCKCHIP_RK3399
|
||||
default 0xfdc20200 if ROCKCHIP_RK3568
|
||||
default 0xfe020200 if ROCKCHIP_RK1808
|
||||
default 0x10300580 if ROCKCHIP_RV1108
|
||||
default 0xfe020200 if ROCKCHIP_RV1126
|
||||
|
|
@ -510,6 +526,7 @@ config ROCKCHIP_STIMER_BASE
|
|||
default 0xff1d0020 if ROCKCHIP_RK3328
|
||||
default 0xff830020 if ROCKCHIP_RK3368
|
||||
default 0xff8680a0 if ROCKCHIP_RK3399
|
||||
default 0xfdd1c020 if ROCKCHIP_RK3568
|
||||
default 0x10350020 if ROCKCHIP_RV1108
|
||||
default 0xff670020 if ROCKCHIP_RV1126
|
||||
default 0
|
||||
|
|
@ -529,6 +546,7 @@ config ROCKCHIP_IRAM_START_ADDR
|
|||
default 0xff091000 if ROCKCHIP_RK3328
|
||||
default 0xff8c0000 if ROCKCHIP_RK3368
|
||||
default 0xff8c0000 if ROCKCHIP_RK3399
|
||||
default 0xfdcc0000 if ROCKCHIP_RK3568
|
||||
default 0x10080000 if ROCKCHIP_RV1108
|
||||
default 0xff700000 if ROCKCHIP_RV1126
|
||||
default 0
|
||||
|
|
@ -763,6 +781,7 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig"
|
|||
source "arch/arm/mach-rockchip/rk3328/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3368/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3399/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3568/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk1808/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rv1108/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rv1126/Kconfig"
|
||||
|
|
|
|||
|
|
@ -63,6 +63,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
|
|||
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
|
||||
obj-$(CONFIG_ROCKCHIP_RK1808) += rk1808/
|
||||
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
|
||||
obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
if ROCKCHIP_RK3568
|
||||
|
||||
config TARGET_EVB_RK3568
|
||||
bool "EVB_RK3568"
|
||||
help
|
||||
RK3568 EVB is a evaluation board for Rockchp RK3568.
|
||||
|
||||
config SYS_SOC
|
||||
default "rockchip"
|
||||
|
||||
config SYS_MALLOC_F_LEN
|
||||
default 0x400
|
||||
|
||||
source board/rockchip/evb_rk3568/Kconfig
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
#
|
||||
# (C) Copyright 2020 Rockchip Electronics Co., Ltd
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += syscon_rk3568.o
|
||||
obj-y += rk3568.o
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/grf_rk3568.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct mm_region rk3568_mem_map[] = {
|
||||
{
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0xf0000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0xf0000000UL,
|
||||
.phys = 0xf0000000UL,
|
||||
.size = 0x10000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = rk3568_mem_map;
|
||||
|
||||
void board_debug_uart_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* (C) Copyright 2020 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
static const struct udevice_id rk3568_syscon_ids[] = {
|
||||
{ .compatible = "rockchip,rk3568-grf", .data = ROCKCHIP_SYSCON_GRF },
|
||||
{ .compatible = "rockchip,rk3568-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(syscon_rk3568) = {
|
||||
.name = "rk3568_syscon",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3568_syscon_ids,
|
||||
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
.bind = dm_scan_fdt_dev,
|
||||
#endif
|
||||
};
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
if TARGET_EVB_RK3568
|
||||
|
||||
config SYS_BOARD
|
||||
default "evb_rk3568"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "rockchip"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "evb_rk3568"
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (c) 2020 Rockchip Electronics Co., Ltd
|
||||
#
|
||||
|
||||
obj-y += evb_rk3568.o
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* (C) Copyright 2020 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright (c) 2020 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#ifndef __CONFIGS_RK3568_EVB_H
|
||||
#define __CONFIGS_RK3568_EVB_H
|
||||
|
||||
#include <configs/rk3568_common.h>
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
||||
#undef ROCKCHIP_DEVICE_SETTINGS
|
||||
#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
|
||||
#undef CONFIG_BOOTCOMMAND
|
||||
#define CONFIG_BOOTCOMMAND RKIMG_BOOTCOMMAND
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2020 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_RK3568_COMMON_H
|
||||
#define __CONFIG_RK3568_COMMON_H
|
||||
|
||||
#include "rockchip-common.h"
|
||||
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00000000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x00020000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000
|
||||
#define CONFIG_SPL_STACK 0x03fe0000
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00600000
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00800800
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
|
||||
#define COUNTER_FREQUENCY 24000000
|
||||
|
||||
#define GICD_BASE 0xfd400000
|
||||
#define GICR_BASE 0xfd460000
|
||||
|
||||
/* MMC/SD IP block */
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
#define CONFIG_SUPPORT_EMMC_RPMB
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0
|
||||
#define SDRAM_MAX_SIZE 0xf0000000
|
||||
#define CONFIG_PREBOOT
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/* usb mass storage */
|
||||
#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
||||
#define CONFIG_ROCKUSB_G_DNL_PID 0x350a
|
||||
|
||||
#define ENV_MEM_LAYOUT_SETTINGS \
|
||||
"scriptaddr=0x00500000\0" \
|
||||
"pxefile_addr_r=0x00600000\0" \
|
||||
"fdt_addr_r=0x01f00000\0" \
|
||||
"kernel_addr_no_bl32_r=0x00280000\0" \
|
||||
"kernel_addr_r=0x00680000\0" \
|
||||
"kernel_addr_c=0x04080000\0" \
|
||||
"ramdisk_addr_r=0x0a200000\0"
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
ENV_MEM_LAYOUT_SETTINGS \
|
||||
"partitions=" PARTS_DEFAULT \
|
||||
ROCKCHIP_DEVICE_SETTINGS \
|
||||
RKIMG_DET_BOOTDEV \
|
||||
BOOTENV
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue