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rockchip: clk: rk322x: support more clks to set and get rate 

Change-Id: Ibed40f1826469263a8015d8af2dea4d3567a08e6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-07-25 16:13:22 +08:00 committed by Kever Yang
parent 0b7db90f19
commit 809e91fd38
3 changed files with 811 additions and 308 deletions
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111
arch/arm/include/asm/arch-rockchip/cru_rk322x.h
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@ -8,27 +8,19 @@
#include <common.h> #include <common.h>
#define MHz 1000000 #define MHz 1000 * 1000
#define OSC_HZ (24 * MHz) #define OSC_HZ (24 * MHz)
#define APLL_HZ (600 * MHz)
#define APLL_HZ (600 * MHz) #define GPLL_HZ (1200 * MHz)
#define GPLL_HZ (594 * MHz) #define CPLL_HZ (500 * MHz)
#define ACLK_BUS_HZ (150 * MHz)
#define CORE_PERI_HZ 150000000 #define ACLK_PERI_HZ (150 * MHz)
#define CORE_ACLK_HZ 300000000
#define BUS_ACLK_HZ 148500000
#define BUS_HCLK_HZ 148500000
#define BUS_PCLK_HZ 74250000
#define PERI_ACLK_HZ 148500000
#define PERI_HCLK_HZ 148500000
#define PERI_PCLK_HZ 74250000
/* Private data for the clock driver - used by rockchip_get_cru() */ /* Private data for the clock driver - used by rockchip_get_cru() */
struct rk322x_clk_priv { struct rk322x_clk_priv {
struct rk322x_cru *cru; struct rk322x_cru *cru;
ulong rate; ulong gpll_hz;
ulong cpll_hz;
}; };
struct rk322x_cru { struct rk322x_cru {
@ -59,57 +51,29 @@ struct rk322x_cru {
}; };
check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
struct pll_div { enum rk322x_pll_id {
u32 refdiv; APLL,
u32 fbdiv; DPLL,
u32 postdiv1; CPLL,
u32 postdiv2; GPLL,
u32 frac; NPLL,
PLL_COUNT,
}; };
struct rk322x_clk_info {
unsigned long id;
char *name;
bool is_cru;
};
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40
enum { enum {
/* PLLCON0*/
PLL_BP_SHIFT = 15,
PLL_POSTDIV1_SHIFT = 12,
PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
PLL_FBDIV_SHIFT = 0,
PLL_FBDIV_MASK = 0xfff,
/* PLLCON1 */
PLL_RST_SHIFT = 14,
PLL_PD_SHIFT = 13,
PLL_PD_MASK = 1 << PLL_PD_SHIFT,
PLL_DSMPD_SHIFT = 12,
PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
PLL_LOCK_STATUS_SHIFT = 10,
PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
PLL_POSTDIV2_SHIFT = 6,
PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
PLL_REFDIV_SHIFT = 0,
PLL_REFDIV_MASK = 0x3f,
/* CRU_MODE */
GPLL_MODE_SHIFT = 12,
GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT,
GPLL_MODE_SLOW = 0,
GPLL_MODE_NORM,
CPLL_MODE_SHIFT = 8,
CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
CPLL_MODE_SLOW = 0,
CPLL_MODE_NORM,
DPLL_MODE_SHIFT = 4,
DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
DPLL_MODE_SLOW = 0,
DPLL_MODE_NORM,
APLL_MODE_SHIFT = 0,
APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
APLL_MODE_SLOW = 0,
APLL_MODE_NORM,
/* CRU_CLK_SEL0_CON */ /* CRU_CLK_SEL0_CON */
BUS_ACLK_PLL_SEL_SHIFT = 13, BUS_ACLK_PLL_SEL_SHIFT = 13,
BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
BUS_ACLK_PLL_SEL_APLL = 0, BUS_ACLK_PLL_SEL_CPLL = 0,
BUS_ACLK_PLL_SEL_GPLL, BUS_ACLK_PLL_SEL_GPLL,
BUS_ACLK_PLL_SEL_HDMIPLL, BUS_ACLK_PLL_SEL_HDMIPLL,
BUS_ACLK_DIV_SHIFT = 8, BUS_ACLK_DIV_SHIFT = 8,
@ -194,15 +158,30 @@ enum {
DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT,
/* CRU_CLKSEL27_CON */ /* CRU_CLKSEL27_CON */
VOP_DCLK_DIV_SHIFT = 8, DCLK_LCDC_PLL_SEL_GPLL = 0,
VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT, DCLK_LCDC_PLL_SEL_CPLL = 1,
VOP_PLL_SEL_SHIFT = 1, DCLK_LCDC_PLL_SEL_SHIFT = 0,
VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT, DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT,
DCLK_LCDC_SEL_HDMIPHY = 0,
DCLK_LCDC_SEL_PLL = 1,
DCLK_LCDC_SEL_SHIFT = 1,
DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT,
DCLK_LCDC_DIV_CON_SHIFT = 8,
DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT,
/* CRU_CLKSEL29_CON */ /* CRU_CLKSEL29_CON */
GMAC_CLK_SRC_SHIFT = 12, GMAC_CLK_SRC_SHIFT = 12,
GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT,
/* CRU_CLKSEL33_CON */
ACLK_VOP_PLL_SEL_SHIFT = 5,
ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
ACLK_VOP_PLL_SEL_CPLL = 0,
ACLK_VOP_PLL_SEL_GPLL = 1,
ACLK_VOP_PLL_SEL_HDMIPHY = 2,
ACLK_VOP_DIV_CON_SHIFT = 0,
ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
/* CRU_SOFTRST5_CON */ /* CRU_SOFTRST5_CON */
DDRCTRL_PSRST_SHIFT = 11, DDRCTRL_PSRST_SHIFT = 11,
DDRCTRL_SRST_SHIFT = 10, DDRCTRL_SRST_SHIFT = 10,

955
drivers/clk/rockchip/clk_rk322x.c
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File diff suppressed because it is too large Load Diff

53
include/dt-bindings/clock/rk3228-cru.h
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@ -40,6 +40,7 @@
#define SCLK_EMMC_DRV 117 #define SCLK_EMMC_DRV 117
#define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDMMC_SAMPLE 118
#define SCLK_SDIO_SAMPLE 119 #define SCLK_SDIO_SAMPLE 119
#define SCLK_SDIO_SRC 120
#define SCLK_EMMC_SAMPLE 121 #define SCLK_EMMC_SAMPLE 121
#define SCLK_VOP 122 #define SCLK_VOP 122
#define SCLK_HDMI_HDCP 123 #define SCLK_HDMI_HDCP 123
@ -52,22 +53,52 @@
#define SCLK_MAC_TX 130 #define SCLK_MAC_TX 130
#define SCLK_MAC_PHY 131 #define SCLK_MAC_PHY 131
#define SCLK_MAC_OUT 132 #define SCLK_MAC_OUT 132
#define SCLK_VDEC_CABAC 133
#define SCLK_VDEC_CORE 134
#define SCLK_RGA 135
#define SCLK_HDCP 136
#define SCLK_HDMI_CEC 137
#define SCLK_CRYPTO 138
#define SCLK_TSP 139
#define SCLK_HSADC 140
#define SCLK_WIFI 141
#define SCLK_OTGPHY0 142
#define SCLK_OTGPHY1 143
#define SCLK_DDRC 144
/* dclk gates */ /* dclk gates */
#define DCLK_VOP 190 #define DCLK_VOP 190
#define DCLK_HDMI_PHY 191 #define DCLK_HDMI_PHY 191
#define HDMIPHY 192
/* aclk gates */ /* aclk gates */
#define ACLK_DMAC 194 #define ACLK_DMAC 194
#define ACLK_CPU 195
#define ACLK_VPU_PRE 196
#define ACLK_RKVDEC_PRE 197
#define ACLK_RGA_PRE 198
#define ACLK_IEP_PRE 199
#define ACLK_HDCP_PRE 200
#define ACLK_VOP_PRE 201
#define ACLK_VPU 202
#define ACLK_RKVDEC 203
#define ACLK_IEP 204
#define ACLK_RGA 205
#define ACLK_HDCP 206
#define ACLK_PERI 210 #define ACLK_PERI 210
#define ACLK_VOP 211 #define ACLK_VOP 211
#define ACLK_GMAC 212 #define ACLK_GMAC 212
#define ACLK_GPU 213
/* pclk gates */ /* pclk gates */
#define PCLK_GPIO0 320 #define PCLK_GPIO0 320
#define PCLK_GPIO1 321 #define PCLK_GPIO1 321
#define PCLK_GPIO2 322 #define PCLK_GPIO2 322
#define PCLK_GPIO3 323 #define PCLK_GPIO3 323
#define PCLK_VIO_H2P 324
#define PCLK_HDCP 325
#define PCLK_EFUSE_1024 326
#define PCLK_EFUSE_256 327
#define PCLK_GRF 329 #define PCLK_GRF 329
#define PCLK_I2C0 332 #define PCLK_I2C0 332
#define PCLK_I2C1 333 #define PCLK_I2C1 333
@ -80,10 +111,12 @@
#define PCLK_TSADC 344 #define PCLK_TSADC 344
#define PCLK_PWM 350 #define PCLK_PWM 350
#define PCLK_TIMER 353 #define PCLK_TIMER 353
#define PCLK_CPU 354
#define PCLK_PERI 363 #define PCLK_PERI 363
#define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_CTRL 364
#define PCLK_HDMI_PHY 365 #define PCLK_HDMI_PHY 365
#define PCLK_GMAC 367 #define PCLK_GMAC 367
#define PCLK_ACODECPHY 368
/* hclk gates */ /* hclk gates */
#define HCLK_I2S0_8CH 442 #define HCLK_I2S0_8CH 442
@ -95,12 +128,28 @@
#define HCLK_SDMMC 456 #define HCLK_SDMMC 456
#define HCLK_SDIO 457 #define HCLK_SDIO 457
#define HCLK_EMMC 459 #define HCLK_EMMC 459
#define HCLK_CPU 460
#define HCLK_VPU_PRE 461
#define HCLK_RKVDEC_PRE 462
#define HCLK_VIO_PRE 463
#define HCLK_VPU 464
#define HCLK_RKVDEC 465
#define HCLK_VIO 466
#define HCLK_RGA 467
#define HCLK_IEP 468
#define HCLK_VIO_H2P 469
#define HCLK_HDCP_MMU 470
#define HCLK_HOST0 471
#define HCLK_HOST1 472
#define HCLK_HOST2 473
#define HCLK_OTG 474
#define HCLK_TSP 475
#define HCLK_M_CRYPTO 476
#define HCLK_S_CRYPTO 477
#define HCLK_PERI 478 #define HCLK_PERI 478
#define CLK_NR_CLKS (HCLK_PERI + 1) #define CLK_NR_CLKS (HCLK_PERI + 1)
#define PCLK_EFUSE_256 327
/* soft-reset indices */ /* soft-reset indices */
#define SRST_CORE0_PO 0 #define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1 #define SRST_CORE1_PO 1