rockchip: clk: rk322x: support more clks to set and get rate
Change-Id: Ibed40f1826469263a8015d8af2dea4d3567a08e6 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
Kever Yang
parent
0b7db90f19
commit
809e91fd38
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@ -8,27 +8,19 @@
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#include <common.h>
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#define MHz 1000000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (594 * MHz)
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#define CORE_PERI_HZ 150000000
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#define CORE_ACLK_HZ 300000000
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#define BUS_ACLK_HZ 148500000
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#define BUS_HCLK_HZ 148500000
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#define BUS_PCLK_HZ 74250000
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#define PERI_ACLK_HZ 148500000
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#define PERI_HCLK_HZ 148500000
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#define PERI_PCLK_HZ 74250000
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#define MHz 1000 * 1000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (1200 * MHz)
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#define CPLL_HZ (500 * MHz)
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#define ACLK_BUS_HZ (150 * MHz)
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#define ACLK_PERI_HZ (150 * MHz)
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk322x_clk_priv {
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struct rk322x_cru *cru;
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ulong rate;
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ulong gpll_hz;
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ulong cpll_hz;
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};
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struct rk322x_cru {
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@ -59,57 +51,29 @@ struct rk322x_cru {
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};
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check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
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struct pll_div {
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u32 refdiv;
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u32 fbdiv;
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u32 postdiv1;
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u32 postdiv2;
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u32 frac;
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enum rk322x_pll_id {
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APLL,
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DPLL,
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CPLL,
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GPLL,
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NPLL,
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PLL_COUNT,
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};
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struct rk322x_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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#define RK2928_PLL_CON(x) ((x) * 0x4)
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#define RK2928_MODE_CON 0x40
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enum {
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/* PLLCON0*/
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PLL_BP_SHIFT = 15,
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PLL_POSTDIV1_SHIFT = 12,
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PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
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PLL_FBDIV_SHIFT = 0,
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PLL_FBDIV_MASK = 0xfff,
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/* PLLCON1 */
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PLL_RST_SHIFT = 14,
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PLL_PD_SHIFT = 13,
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PLL_PD_MASK = 1 << PLL_PD_SHIFT,
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PLL_DSMPD_SHIFT = 12,
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PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
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PLL_LOCK_STATUS_SHIFT = 10,
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PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
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PLL_POSTDIV2_SHIFT = 6,
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PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
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PLL_REFDIV_SHIFT = 0,
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PLL_REFDIV_MASK = 0x3f,
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/* CRU_MODE */
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GPLL_MODE_SHIFT = 12,
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GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT,
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GPLL_MODE_SLOW = 0,
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GPLL_MODE_NORM,
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CPLL_MODE_SHIFT = 8,
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CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
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CPLL_MODE_SLOW = 0,
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CPLL_MODE_NORM,
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DPLL_MODE_SHIFT = 4,
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DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
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DPLL_MODE_SLOW = 0,
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DPLL_MODE_NORM,
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APLL_MODE_SHIFT = 0,
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APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
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APLL_MODE_SLOW = 0,
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APLL_MODE_NORM,
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/* CRU_CLK_SEL0_CON */
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BUS_ACLK_PLL_SEL_SHIFT = 13,
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BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
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BUS_ACLK_PLL_SEL_APLL = 0,
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BUS_ACLK_PLL_SEL_CPLL = 0,
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BUS_ACLK_PLL_SEL_GPLL,
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BUS_ACLK_PLL_SEL_HDMIPLL,
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BUS_ACLK_DIV_SHIFT = 8,
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@ -194,15 +158,30 @@ enum {
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DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT,
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/* CRU_CLKSEL27_CON */
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VOP_DCLK_DIV_SHIFT = 8,
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VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT,
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VOP_PLL_SEL_SHIFT = 1,
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VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT,
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DCLK_LCDC_PLL_SEL_GPLL = 0,
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DCLK_LCDC_PLL_SEL_CPLL = 1,
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DCLK_LCDC_PLL_SEL_SHIFT = 0,
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DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT,
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DCLK_LCDC_SEL_HDMIPHY = 0,
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DCLK_LCDC_SEL_PLL = 1,
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DCLK_LCDC_SEL_SHIFT = 1,
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DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT,
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DCLK_LCDC_DIV_CON_SHIFT = 8,
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DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT,
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/* CRU_CLKSEL29_CON */
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GMAC_CLK_SRC_SHIFT = 12,
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GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT,
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/* CRU_CLKSEL33_CON */
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ACLK_VOP_PLL_SEL_SHIFT = 5,
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ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
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ACLK_VOP_PLL_SEL_CPLL = 0,
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ACLK_VOP_PLL_SEL_GPLL = 1,
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ACLK_VOP_PLL_SEL_HDMIPHY = 2,
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ACLK_VOP_DIV_CON_SHIFT = 0,
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ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
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/* CRU_SOFTRST5_CON */
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DDRCTRL_PSRST_SHIFT = 11,
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DDRCTRL_SRST_SHIFT = 10,
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File diff suppressed because it is too large
Load Diff
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@ -40,6 +40,7 @@
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#define SCLK_EMMC_DRV 117
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_SDIO_SRC 120
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_VOP 122
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#define SCLK_HDMI_HDCP 123
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@ -52,22 +53,52 @@
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#define SCLK_MAC_TX 130
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#define SCLK_MAC_PHY 131
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#define SCLK_MAC_OUT 132
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#define SCLK_VDEC_CABAC 133
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#define SCLK_VDEC_CORE 134
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#define SCLK_RGA 135
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#define SCLK_HDCP 136
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#define SCLK_HDMI_CEC 137
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#define SCLK_CRYPTO 138
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#define SCLK_TSP 139
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#define SCLK_HSADC 140
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#define SCLK_WIFI 141
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#define SCLK_OTGPHY0 142
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#define SCLK_OTGPHY1 143
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#define SCLK_DDRC 144
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/* dclk gates */
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#define DCLK_VOP 190
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#define DCLK_HDMI_PHY 191
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#define HDMIPHY 192
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/* aclk gates */
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#define ACLK_DMAC 194
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#define ACLK_CPU 195
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#define ACLK_VPU_PRE 196
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#define ACLK_RKVDEC_PRE 197
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#define ACLK_RGA_PRE 198
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#define ACLK_IEP_PRE 199
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#define ACLK_HDCP_PRE 200
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#define ACLK_VOP_PRE 201
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#define ACLK_VPU 202
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#define ACLK_RKVDEC 203
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#define ACLK_IEP 204
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#define ACLK_RGA 205
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#define ACLK_HDCP 206
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#define ACLK_PERI 210
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#define ACLK_VOP 211
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#define ACLK_GMAC 212
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#define ACLK_GPU 213
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/* pclk gates */
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#define PCLK_GPIO0 320
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#define PCLK_GPIO1 321
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#define PCLK_GPIO2 322
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#define PCLK_GPIO3 323
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#define PCLK_VIO_H2P 324
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#define PCLK_HDCP 325
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#define PCLK_EFUSE_1024 326
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#define PCLK_EFUSE_256 327
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#define PCLK_GRF 329
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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@ -80,10 +111,12 @@
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#define PCLK_TSADC 344
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#define PCLK_PWM 350
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#define PCLK_TIMER 353
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#define PCLK_CPU 354
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#define PCLK_PERI 363
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#define PCLK_HDMI_CTRL 364
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#define PCLK_HDMI_PHY 365
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#define PCLK_GMAC 367
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#define PCLK_ACODECPHY 368
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/* hclk gates */
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#define HCLK_I2S0_8CH 442
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@ -95,12 +128,28 @@
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#define HCLK_SDMMC 456
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#define HCLK_SDIO 457
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#define HCLK_EMMC 459
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#define HCLK_CPU 460
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#define HCLK_VPU_PRE 461
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#define HCLK_RKVDEC_PRE 462
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#define HCLK_VIO_PRE 463
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#define HCLK_VPU 464
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#define HCLK_RKVDEC 465
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#define HCLK_VIO 466
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#define HCLK_RGA 467
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#define HCLK_IEP 468
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#define HCLK_VIO_H2P 469
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#define HCLK_HDCP_MMU 470
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#define HCLK_HOST0 471
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#define HCLK_HOST1 472
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#define HCLK_HOST2 473
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#define HCLK_OTG 474
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#define HCLK_TSP 475
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#define HCLK_M_CRYPTO 476
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#define HCLK_S_CRYPTO 477
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#define HCLK_PERI 478
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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#define PCLK_EFUSE_256 327
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/* soft-reset indices */
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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