regulator: rk8xx: add ops->set_ramp_delay() implement
Change-Id: I8c7b7fad8c966d2fff8e2b0cf80ff59b6f70b57b Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This commit is contained in:
Joseph Chen
Kever Yang
parent
b29e2b63a9
commit
868bdcf383
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@ -41,6 +41,7 @@
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#define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * (n - 1))
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#define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * (n - 1))
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#define RK817_BUCK_VSEL_MASK 0x7f
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#define RK817_BUCK_CONFIG(i) (0xba + (i) * 3)
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/* RK817 LDO */
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#define RK817_LDO_ON_VSEL(n) (0xcc + 2 * (n - 1))
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@ -51,69 +52,94 @@
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#define RK817_POWER_EN(n) (0xb1 + (n))
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#define RK817_POWER_SLP_EN(n) (0xb5 + (n))
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/*
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* Ramp delay
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*/
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#define RK805_RAMP_RATE_OFFSET 3
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#define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET)
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#define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET)
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#define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET)
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#define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET)
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#define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET)
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#define RK808_RAMP_RATE_OFFSET 3
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#define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET)
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#define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET)
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#define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET)
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#define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET)
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#define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET)
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#define RK817_RAMP_RATE_OFFSET 6
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#define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET)
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#define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET)
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#define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET)
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#define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET)
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#define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET)
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struct rk8xx_reg_info {
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uint min_uv;
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uint step_uv;
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u8 vsel_reg;
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u8 vsel_sleep_reg;
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u8 config_reg;
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u8 vsel_mask;
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u8 min_sel;
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};
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static const struct rk8xx_reg_info rk808_buck[] = {
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{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK808_BUCK_VSEL_MASK, },
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{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK808_BUCK_VSEL_MASK, },
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{ 712500, 12500, -1, -1, RK808_BUCK_VSEL_MASK, },
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{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, RK808_BUCK4_VSEL_MASK, },
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{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, },
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{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, },
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{ 712500, 12500, -1, -1, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, },
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{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, },
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};
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static const struct rk8xx_reg_info rk816_buck[] = {
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/* buck 1 */
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{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK818_BUCK_VSEL_MASK, 0x00, },
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{ 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK818_BUCK_VSEL_MASK, 0x3c, },
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{ 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK818_BUCK_VSEL_MASK, 0x3f, },
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{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
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{ 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
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{ 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
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/* buck 2 */
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{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK818_BUCK_VSEL_MASK, 0x00, },
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{ 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK818_BUCK_VSEL_MASK, 0x3c, },
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{ 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK818_BUCK_VSEL_MASK, 0x3f, },
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{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
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{ 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
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{ 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
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/* buck 3 */
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{ 712500, 12500, -1, -1, RK818_BUCK_VSEL_MASK, },
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{ 712500, 12500, -1, -1, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
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/* buck 4 */
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{ 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, RK818_BUCK4_VSEL_MASK, },
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{ 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
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};
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static const struct rk8xx_reg_info rk809_buck5[] = {
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/* buck 5 */
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{ 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), RK809_BUCK5_VSEL_MASK, 0x00, },
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{ 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), RK809_BUCK5_VSEL_MASK, 0x01, },
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{ 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), RK809_BUCK5_VSEL_MASK, 0x04, },
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{ 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), RK809_BUCK5_VSEL_MASK, 0x06, },
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{ 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), -1, RK809_BUCK5_VSEL_MASK, 0x00, },
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{ 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), -1, RK809_BUCK5_VSEL_MASK, 0x01, },
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{ 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), -1, RK809_BUCK5_VSEL_MASK, 0x04, },
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{ 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), -1, RK809_BUCK5_VSEL_MASK, 0x06, },
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};
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static const struct rk8xx_reg_info rk817_buck[] = {
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/* buck 1 */
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{ 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_VSEL_MASK, 0x00, },
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{ 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_VSEL_MASK, 0x50, },
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{ 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_VSEL_MASK, 0x59, },
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{ 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, },
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{ 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, },
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{ 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, },
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/* buck 2 */
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{ 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_VSEL_MASK, 0x00, },
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{ 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_VSEL_MASK, 0x50, },
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{ 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_VSEL_MASK, 0x59, },
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{ 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, },
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{ 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, },
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{ 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, },
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/* buck 3 */
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{ 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_VSEL_MASK, 0x00, },
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{ 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_VSEL_MASK, 0x50, },
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{ 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_VSEL_MASK, 0x59, },
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{ 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, },
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{ 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, },
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{ 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, },
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/* buck 4 */
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{ 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_VSEL_MASK, 0x00, },
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{ 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_VSEL_MASK, 0x50, },
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{ 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_VSEL_MASK, 0x63, },
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{ 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, },
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{ 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, },
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{ 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, },
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};
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static const struct rk8xx_reg_info rk818_buck[] = {
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{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, RK818_BUCK_VSEL_MASK, },
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{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, RK818_BUCK_VSEL_MASK, },
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{ 712500, 12500, -1, -1, RK818_BUCK_VSEL_MASK, },
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{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, RK818_BUCK4_VSEL_MASK, },
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{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, },
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{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, },
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{ 712500, 12500, -1, -1, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
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{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
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};
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#ifdef ENABLE_DRIVER
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@ -389,6 +415,89 @@ static int _buck_get_enable(struct udevice *pmic, int buck)
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return ret & mask ? true : false;
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}
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static int _buck_set_ramp_delay(struct udevice *pmic, int buck, u32 ramp_delay)
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{
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const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, 0);
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struct rk8xx_priv *priv = dev_get_priv(pmic);
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u32 ramp_value, ramp_mask;
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if (info->config_reg == -1)
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return -ENOSYS;
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switch (priv->variant) {
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case RK805_ID:
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ramp_mask = RK805_RAMP_RATE_MASK;
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ramp_value = RK805_RAMP_RATE_12_5MV_PER_US;
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switch (ramp_delay) {
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case 0 ... 3000:
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ramp_value = RK805_RAMP_RATE_3MV_PER_US;
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break;
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case 3001 ... 6000:
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ramp_value = RK805_RAMP_RATE_6MV_PER_US;
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break;
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case 6001 ... 12500:
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ramp_value = RK805_RAMP_RATE_12_5MV_PER_US;
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break;
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case 12501 ... 25000:
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ramp_value = RK805_RAMP_RATE_25MV_PER_US;
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break;
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default:
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printf("buck%d ramp_delay: %d not supported\n",
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buck, ramp_delay);
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}
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break;
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case RK808_ID:
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case RK816_ID:
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case RK818_ID:
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ramp_value = RK808_RAMP_RATE_6MV_PER_US;
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ramp_mask = RK808_RAMP_RATE_MASK;
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switch (ramp_delay) {
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case 1 ... 2000:
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ramp_value = RK808_RAMP_RATE_2MV_PER_US;
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break;
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case 2001 ... 4000:
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ramp_value = RK808_RAMP_RATE_4MV_PER_US;
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break;
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case 4001 ... 6000:
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ramp_value = RK808_RAMP_RATE_6MV_PER_US;
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break;
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case 6001 ... 10000:
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ramp_value = RK808_RAMP_RATE_6MV_PER_US;
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break;
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default:
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printf("buck%d ramp_delay: %d not supported\n",
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buck, ramp_delay);
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}
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break;
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case RK809_ID:
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case RK817_ID:
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ramp_mask = RK817_RAMP_RATE_MASK;
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ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
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switch (ramp_delay) {
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case 0 ... 3000:
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ramp_value = RK817_RAMP_RATE_3MV_PER_US;
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break;
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case 3001 ... 6300:
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ramp_value = RK817_RAMP_RATE_6_3MV_PER_US;
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break;
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case 6301 ... 12500:
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ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
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break;
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case 12501 ... 25000:
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ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
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break;
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default:
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printf("buck%d ramp_delay: %d not supported\n",
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buck, ramp_delay);
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}
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break;
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default:
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return -EINVAL;
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}
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return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value);
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}
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static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable)
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{
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uint mask;
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@ -628,6 +737,13 @@ static int buck_set_suspend_enable(struct udevice *dev, bool enable)
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return _buck_set_suspend_enable(dev->parent, buck, enable);
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}
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static int buck_set_ramp_delay(struct udevice *dev, u32 ramp_delay)
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{
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int buck = dev->driver_data - 1;
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return _buck_set_ramp_delay(dev->parent, buck, ramp_delay);
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}
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static int buck_get_enable(struct udevice *dev)
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{
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int buck = dev->driver_data - 1;
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@ -850,6 +966,7 @@ static const struct dm_regulator_ops rk8xx_buck_ops = {
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.get_enable = buck_get_enable,
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.set_enable = buck_set_enable,
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.set_suspend_enable = buck_set_suspend_enable,
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.set_ramp_delay = buck_set_ramp_delay,
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};
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static const struct dm_regulator_ops rk8xx_ldo_ops = {
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