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clk: rockchip: rk3399: fix up the assert error 

Change-Id: I8cc4f6b775243fef1f5c8e2c711eb1b16eac79a8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-04-18 16:30:13 +08:00 committed by Kever Yang
parent f25e3caf73
commit 88c36f1205
1 changed files with 9 additions and 9 deletions
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18
drivers/clk/rockchip/clk_rk3399.c
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@ -534,15 +534,15 @@ void rk3399_configure_cpu(struct rk3399_cru *cru,
rkclk_set_pll(pll_con, apll_cfgs[freq]);
aclkm_div = apll_hz / ACLKM_CORE_HZ - 1;
assert((aclkm_div + 1) * ACLKM_CORE_HZ == apll_hz &&
assert((aclkm_div + 1) * ACLKM_CORE_HZ <= apll_hz &&
aclkm_div < 0x1f);
pclk_dbg_div = apll_hz / PCLK_DBG_HZ - 1;
assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == apll_hz &&
assert((pclk_dbg_div + 1) * PCLK_DBG_HZ <= apll_hz &&
pclk_dbg_div < 0x1f);
atclk_div = apll_hz / ATCLK_CORE_HZ - 1;
assert((atclk_div + 1) * ATCLK_CORE_HZ == apll_hz &&
assert((atclk_div + 1) * ATCLK_CORE_HZ <= apll_hz &&
atclk_div < 0x1f);
rk_clrsetreg(&cru->clksel_con[con_base],
@ -1416,11 +1416,11 @@ static void rkclk_init(struct rk3399_cru *cru)
aclk_div = DIV_ROUND_UP(GPLL_HZ, PERIHP_ACLK_HZ) - 1;
hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
assert((hclk_div + 1) * PERIHP_HCLK_HZ <=
PERIHP_ACLK_HZ && (hclk_div <= 0x3));
pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
assert((pclk_div + 1) * PERIHP_PCLK_HZ <=
PERIHP_ACLK_HZ && (pclk_div <= 0x7));
rk_clrsetreg(&cru->clksel_con[14],
@ -1435,11 +1435,11 @@ static void rkclk_init(struct rk3399_cru *cru)
aclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP0_ACLK_HZ) - 1;
hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
assert((hclk_div + 1) * PERILP0_HCLK_HZ <=
PERILP0_ACLK_HZ && (hclk_div <= 0x3));
pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
assert((pclk_div + 1) * PERILP0_PCLK_HZ <=
PERILP0_ACLK_HZ && (pclk_div <= 0x7));
rk_clrsetreg(&cru->clksel_con[23],
@ -1452,11 +1452,11 @@ static void rkclk_init(struct rk3399_cru *cru)
/* perilp1 hclk select gpll as source */
hclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP1_HCLK_HZ) - 1;
assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
assert((hclk_div + 1) * PERILP1_HCLK_HZ <=
GPLL_HZ && (hclk_div <= 0x1f));
pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1;
assert((pclk_div + 1) * PERILP1_PCLK_HZ ==
assert((pclk_div + 1) * PERILP1_PCLK_HZ <=
PERILP1_HCLK_HZ && (pclk_div <= 0x7));
rk_clrsetreg(&cru->clksel_con[25],