dm: reset: add reset support for SPL
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I8210b7f656b99bf7cbf4a6708696ebbf91aa7685
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381f27a639
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@ -103,7 +103,6 @@ obj-$(CONFIG_U_QE) += qe/
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obj-y += mailbox/
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obj-y += mailbox/
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obj-y += memory/
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obj-y += memory/
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obj-y += pwm/
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obj-y += pwm/
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obj-y += reset/
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obj-y += input/
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obj-y += input/
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# SOC specific infrastructure drivers.
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# SOC specific infrastructure drivers.
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obj-y += soc/
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obj-y += soc/
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@ -112,3 +111,6 @@ obj-y += thermal/
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obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
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obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
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endif
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endif
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obj-$(CONFIG_$(SPL_TPL_)DM_RESET) += reset/
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@ -12,6 +12,18 @@ config DM_RESET
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although driving such reset isgnals using GPIOs may be more
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although driving such reset isgnals using GPIOs may be more
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appropriate in this case.
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appropriate in this case.
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config SPL_DM_RESET
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bool "Enable reset controllers using Driver Model in SPL"
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depends on SPL_DM && OF_CONTROL
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help
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Enable support for the reset controller driver class. Many hardware
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modules are equipped with a reset signal, typically driven by some
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reset controller hardware module within the chip. In U-Boot, reset
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controller drivers allow control over these reset signals. In some
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cases this API is applicable to chips outside the CPU as well,
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although driving such reset isgnals using GPIOs may be more
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appropriate in this case.
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config SANDBOX_RESET
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config SANDBOX_RESET
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bool "Enable the sandbox reset test driver"
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bool "Enable the sandbox reset test driver"
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depends on DM_MAILBOX && SANDBOX
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depends on DM_MAILBOX && SANDBOX
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@ -75,4 +87,10 @@ config RESET_ROCKCHIP
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Support for reset controller on rockchip SoC. The main limitation though
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Support for reset controller on rockchip SoC. The main limitation though
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is that some reset signals, like I2C or MISC reset multiple devices.
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is that some reset signals, like I2C or MISC reset multiple devices.
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config SPL_RESET_ROCKCHIP
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bool "Reset controller driver for Rockchip SoCs in SPL"
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depends on SPL_DM_RESET && SPL_CLK
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help
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Support for reset controller on rockchip SoC. The main limitation though
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is that some reset signals, like I2C or MISC reset multiple devices.
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endmenu
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endmenu
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@ -2,7 +2,7 @@
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#
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#
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# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_DM_RESET) += reset-uclass.o
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obj-$(CONFIG_$(SPL_)DM_RESET) += reset-uclass.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
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obj-$(CONFIG_STI_RESET) += sti-reset.o
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obj-$(CONFIG_STI_RESET) += sti-reset.o
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@ -11,4 +11,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
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obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
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obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
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obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
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obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
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obj-$(CONFIG_$(SPL_)RESET_ROCKCHIP) += reset-rockchip.o
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