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clk: rockchip: rk3036: add nandc clk init 

Change-Id: I8aefe310a366e346310135f684f3b5db43b0b734
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Elaine Zhang 2020-03-11 16:21:08 +08:00 committed by Jon Lin
parent ddf875ab3d
commit 904b267d4b
2 changed files with 17 additions and 0 deletions
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9
arch/arm/include/asm/arch-rockchip/cru_rk3036.h
View File

@ -178,6 +178,15 @@ enum {
EMMC_DIV_SHIFT = 0,
EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT,
/* CRU_CLKSEL16_CON */
NANDC_DIV_SHIFT = 10,
NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT,
NANDC_PLL_SHIFT = 8,
NANDC_PLL_MASK = 3 << NANDC_PLL_SHIFT,
NANDC_SEL_APLL = 0,
NANDC_SEL_DPLL,
NANDC_SEL_GPLL,
/* CRU_SOFTRST5_CON */
DDRCTRL_PSRST_SHIFT = 11,
DDRCTRL_SRST_SHIFT = 10,

8
drivers/clk/rockchip/clk_rk3036.c
View File

@ -104,6 +104,7 @@ static void rkclk_init(struct rk3036_cru *cru)
u32 aclk_div;
u32 hclk_div;
u32 pclk_div;
u32 nandc_div;
/* pll enter slow-mode */
rk_clrsetreg(&cru->cru_mode_con,
@ -182,6 +183,13 @@ static void rkclk_init(struct rk3036_cru *cru)
hclk_div << PERI_HCLK_DIV_SHIFT |
aclk_div << PERI_ACLK_DIV_SHIFT);
nandc_div = DIV_ROUND_UP(GPLL_HZ, 150 * 1000000);
rk_clrsetreg(&cru->cru_clksel_con[16],
NANDC_PLL_MASK | NANDC_DIV_MASK,
NANDC_SEL_GPLL << NANDC_PLL_SHIFT |
nandc_div << NANDC_DIV_SHIFT);
/* PLL enter normal-mode */
rk_clrsetreg(&cru->cru_mode_con,
GPLL_MODE_MASK | APLL_MODE_MASK,