diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
index d908d9460f..572138171e 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
@@ -178,6 +178,15 @@ enum {
 	EMMC_DIV_SHIFT		= 0,
 	EMMC_DIV_MASK		= 0x7f << EMMC_DIV_SHIFT,
 
+	/* CRU_CLKSEL16_CON */
+	NANDC_DIV_SHIFT		= 10,
+	NANDC_DIV_MASK		= 0x1f << NANDC_DIV_SHIFT,
+	NANDC_PLL_SHIFT		= 8,
+	NANDC_PLL_MASK		= 3 << NANDC_PLL_SHIFT,
+	NANDC_SEL_APLL		= 0,
+	NANDC_SEL_DPLL,
+	NANDC_SEL_GPLL,
+
 	/* CRU_SOFTRST5_CON */
 	DDRCTRL_PSRST_SHIFT	= 11,
 	DDRCTRL_SRST_SHIFT	= 10,
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 4b242b4b7b..b7c93584ec 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -104,6 +104,7 @@ static void rkclk_init(struct rk3036_cru *cru)
 	u32 aclk_div;
 	u32 hclk_div;
 	u32 pclk_div;
+	u32 nandc_div;
 
 	/* pll enter slow-mode */
 	rk_clrsetreg(&cru->cru_mode_con,
@@ -182,6 +183,13 @@ static void rkclk_init(struct rk3036_cru *cru)
 		     hclk_div << PERI_HCLK_DIV_SHIFT |
 		     aclk_div << PERI_ACLK_DIV_SHIFT);
 
+	nandc_div = DIV_ROUND_UP(GPLL_HZ, 150 * 1000000);
+
+	rk_clrsetreg(&cru->cru_clksel_con[16],
+		     NANDC_PLL_MASK | NANDC_DIV_MASK,
+		     NANDC_SEL_GPLL << NANDC_PLL_SHIFT |
+		     nandc_div << NANDC_DIV_SHIFT);
+
 	/* PLL enter normal-mode */
 	rk_clrsetreg(&cru->cru_mode_con,
 		     GPLL_MODE_MASK | APLL_MODE_MASK,