driver: ram: rockchip: update the driver of sdram_pctl_px30
Change-Id: I586065b41a22bbee266fa234e6513ef1dac5b37b Signed-off-by: YouMin Chen <cym@rock-chips.com>
This commit is contained in:
YouMin Chen
parent
0e03287145
commit
9442a4b3bb
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@ -8,7 +8,7 @@
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#include <asm/arch/sdram_common.h>
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struct ddr_pctl_regs {
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u32 pctl[30][2];
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u32 pctl[35][2];
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};
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/* ddr pctl registers define */
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@ -21,6 +21,7 @@ struct ddr_pctl_regs {
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#define DDR_PCTL2_MRCTRL2 0x1c
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#define DDR_PCTL2_DERATEEN 0x20
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#define DDR_PCTL2_DERATEINT 0x24
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#define DDR_PCTL2_MSTR2 0x28
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#define DDR_PCTL2_PWRCTL 0x30
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#define DDR_PCTL2_PWRTMG 0x34
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#define DDR_PCTL2_HWLPCTL 0x38
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@ -118,8 +119,100 @@ struct ddr_pctl_regs {
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#define DDR_PCTL2_PCFGW_n 0x408
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#define DDR_PCTL2_PCTRL_n 0x490
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#define UMCTL2_REGS_FREQ(n) \
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((0x1000 * (n) + (((n) > 0) ? 0x1000 : 0)))
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/* PCTL2_MRSTAT */
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#define MR_WR_BUSY BIT(0)
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#define PCTL2_FREQUENCY_MODE_MASK (1)
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#define PCTL2_FREQUENCY_MODE_SHIFT (29)
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#define PCTL2_DLL_OFF_MODE BIT(15)
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#define PCTL2_MR_WR_BUSY BIT(0)
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/* PCTL2_STAT */
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#define PCTL2_SELFREF_TYPE_MASK (3 << 4)
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#define PCTL2_SELFREF_TYPE_SR_NOT_AUTO (2 << 4)
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#define PCTL2_OPERATING_MODE_MASK (7)
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#define PCTL2_OPERATING_MODE_INIT (1)
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#define PCTL2_OPERATING_MODE_SR (3)
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/* PCTL2_MRCTRL0 */
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#define PCTL2_MR_WR BIT(31)
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#define PCTL2_MR_ADDR_SHIFT (12)
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#define PCTL2_MR_RANK_SHIFT (4)
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#define PCTL2_MR_TYPE_WR (0)
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#define PCTL2_MR_TYPE_RD (1)
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/* PCTL2_MRCTRL1 */
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#define PCTL2_MR_ADDRESS_SHIFT (8)
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#define PCTL2_MR_DATA_MASK (0xff)
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/* PCTL2_DERATEEN */
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#define PCTL2_DERATE_ENABLE (1)
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/* PCTL2_PWRCTL */
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#define PCTL2_SELFREF_SW BIT(5)
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#define PCTL2_POWERDOWN_EN BIT(1)
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#define PCTL2_SELFREF_EN (1)
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/* PCTL2_PWRTMG */
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#define PCTL2_SELFREF_TO_X32_MASK (0xFF)
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#define PCTL2_SELFREF_TO_X32_SHIFT (16)
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#define PCTL2_POWERDOWN_TO_X32_MASK (0x1F)
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/* PCTL2_INIT3 */
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#define PCTL2_DDR34_MR0_SHIFT (16)
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#define PCTL2_LPDDR234_MR1_SHIFT (16)
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#define PCTL2_DDR34_MR1_SHIFT (0)
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#define PCTL2_LPDDR234_MR2_SHIFT (0)
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/* PCTL2_INIT4 */
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#define PCTL2_DDR34_MR2_SHIFT (16)
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#define PCTL2_LPDDR234_MR3_SHIFT (16)
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#define PCTL2_DDR34_MR3_SHIFT (0)
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#define PCTL2_LPDDR4_MR13_SHIFT (0)
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/* PCTL2_INIT6 */
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#define PCTL2_DDR4_MR4_SHIFT (16)
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#define PCTL2_LPDDR4_MR11_SHIFT (16)
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#define PCTL2_DDR4_MR5_SHIFT (0)
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#define PCTL2_LPDDR4_MR12_SHIFT (0)
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/* PCTL2_INIT7 */
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#define PCTL2_LPDDR4_MR22_SHIFT (16)
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#define PCTL2_DDR4_MR6_SHIFT (0)
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#define PCTL2_LPDDR4_MR14_SHIFT (0)
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#define PCTL2_MR_MASK (0xffff)
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/* PCTL2_RFSHCTL3 */
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#define PCTL2_DIS_AUTO_REFRESH (1)
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/* PCTL2_ZQCTL0 */
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#define PCTL2_DIS_AUTO_ZQ BIT(31)
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#define PCTL2_DIS_SRX_ZQCL BIT(30)
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/* PCTL2_DFILPCFG0 */
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#define PCTL2_DFI_LP_EN_SR BIT(8)
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#define PCTL2_DFI_LP_EN_SR_MASK BIT(8)
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#define PCTL2_DFI_LP_EN_SR_SHIFT (8)
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/* PCTL2_DFIMISC */
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#define PCTL2_DFI_INIT_COMPLETE_EN (1)
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/* PCTL2_DFISTAT */
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#define PCTL2_DFI_LP_ACK BIT(1)
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#define PCTL2_DFI_INIT_COMPLETE (1)
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/* PCTL2_DBG1 */
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#define PCTL2_DIS_HIF BIT(1)
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/* PCTL2_DBGCAM */
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#define PCTL2_DBG_WR_Q_EMPTY BIT(26)
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#define PCTL2_DBG_RD_Q_EMPTY BIT(25)
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#define PCTL2_DBG_LPR_Q_DEPTH_MASK (0xffff << 8)
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#define PCTL2_DBG_LPR_Q_DEPTH_EMPTY (0x0 << 8)
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/* PCTL2_DBGCMD */
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#define PCTL2_RANK1_REFRESH BIT(1)
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#define PCTL2_RANK0_REFRESH (1)
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/* PCTL2_DBGSTAT */
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#define PCTL2_RANK1_REFRESH_BUSY BIT(1)
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#define PCTL2_RANK0_REFRESH_BUSY (1)
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/* PCTL2_SWCTL */
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#define PCTL2_SW_DONE (1)
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#define PCTL2_SW_DONE_CLEAR (0)
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/* PCTL2_SWSTAT */
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#define PCTL2_SW_DONE_ACK (1)
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/* PCTL2_PSTAT */
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#define PCTL2_WR_PORT_BUSY_0 BIT(16)
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#define PCTL2_RD_PORT_BUSY_0 (1)
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/* PCTL2_PCTRLn */
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#define PCTL2_PORT_EN (1)
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void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num);
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int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
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@ -20,7 +20,7 @@ void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num)
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setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
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while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
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continue;
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while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
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while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)
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continue;
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}
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@ -32,7 +32,7 @@ void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num)
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int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
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u32 dramtype)
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{
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while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
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while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)
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continue;
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if (dramtype == DDR3 || dramtype == DDR4) {
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writel((mr_num << 12) | (rank << 4) | (0 << 0),
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@ -48,7 +48,7 @@ int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
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setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
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while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
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continue;
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while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
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while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)
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continue;
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return 0;
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@ -64,8 +64,7 @@ int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
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u32 tccd_l, value;
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u32 dis_auto_zq = 0;
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if (dramtype != DDR4 || vrefrate < 4500 ||
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vrefrate > 9200)
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if (dramtype != DDR4 || vrefrate < 4500 || vrefrate > 9250)
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return (-1);
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tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
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@ -164,16 +163,8 @@ u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs,
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break;
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}
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/*
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* If DDR3 or DDR4 MSTR.active_ranks=1,
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* it will gate memory clock when enter power down.
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* Force set active_ranks to 3 to workaround it.
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*/
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if (cap_info->rank == 2 || dram_type == DDR3 ||
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dram_type == DDR4)
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tmp |= 3 << 24;
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else
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tmp |= 1 << 24;
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/* active_ranks always keep 2 rank for dfi monitor */
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tmp |= 3 << 24;
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tmp |= (2 - cap_info->bw) << 12;
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