diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c
index 0c36a2767c..ff4574cbad 100644
--- a/arch/arm/mach-rockchip/rv1126/rv1126.c
+++ b/arch/arm/mach-rockchip/rv1126/rv1126.c
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/grf_rv1126.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,6 +53,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define CRU_BASE		0xFF490000
 #define CRU_SOFTRST_CON02	0x308
+#define GRF_BASE		0xFE000000
+#define PMUGRF_BASE		0xFE020000
 #define SGRF_BASE		0xFE0A0000
 #define SGRF_CON_SCR1_BOOT_ADDR	0x0b0
 #define SGRF_SOC_CON3		0x00c
@@ -60,9 +63,442 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PMUGRF_SOC_CON1		0xFE020104
 #define GRF_IOFUNC_CON3		0xFF01026C
 
+enum {
+	GPIO1A7_SHIFT		= 12,
+	GPIO1A7_MASK		= GENMASK(14, 12),
+	GPIO1A7_GPIO		= 0,
+	GPIO1A7_SDMMC0_D3,
+	GPIO1A7_UART3_TX_M1,
+	GPIO1A7_A7_JTAG_TMS_M0,
+	GPIO1A7_RISCV_JTAG_TMS,
+
+	GPIO1A6_SHIFT		= 8,
+	GPIO1A6_MASK		= GENMASK(10, 8),
+	GPIO1A6_GPIO		= 0,
+	GPIO1A6_SDMMC0_D2,
+	GPIO1A6_UART3_RX_M1,
+	GPIO1A6_A7_JTAG_TCK_M0,
+	GPIO1A6_RISCV_JTAG_TCK,
+
+	GPIO1A5_SHIFT		= 4,
+	GPIO1A5_MASK		= GENMASK(6, 4),
+	GPIO1A5_GPIO		= 0,
+	GPIO1A5_SDMMC0_D1,
+	GPIO1A5_TEST_CLK0_OUT,
+	GPIO1A5_UART2_TX_M0,
+	GPIO1A5_RISCV_JTAG_TRSTN,
+
+	GPIO1A4_SHIFT		= 0,
+	GPIO1A4_MASK		= GENMASK(2, 0),
+	GPIO1A4_GPIO		= 0,
+	GPIO1A4_SDMMC0_D0,
+	GPIO1A4_TEST_CLK1_OUT,
+	GPIO1A4_UART2_RX_M0,
+
+	GPIO1C3_SHIFT		= 12,
+	GPIO1C3_MASK		= GENMASK(14, 12),
+	GPIO1C3_GPIO		= 0,
+	GPIO1C3_UART0_TX,
+
+	GPIO1C2_SHIFT		= 8,
+	GPIO1C2_MASK		= GENMASK(10, 8),
+	GPIO1C2_GPIO		= 0,
+	GPIO1C2_UART0_RX,
+
+	GPIO1D5_SHIFT		= 4,
+	GPIO1D5_MASK		= GENMASK(6, 4),
+	GPIO1D5_GPIO		= 0,
+	GPIO1D5_SPI0_CS1N_M1,
+	GPIO1D5_I2S1_MCLK_M1,
+	GPIO1D5_UART4_TX_M2,
+
+	GPIO1D4_SHIFT		= 0,
+	GPIO1D4_MASK		= GENMASK(2, 0),
+	GPIO1D4_GPIO		= 0,
+	GPIO1D4_RESERVED0,
+	GPIO1D4_RESERVED1,
+	GPIO1D4_UART4_RX_M2,
+
+	GPIO1D1_SHIFT		= 4,
+	GPIO1D1_MASK		= GENMASK(6, 4),
+	GPIO1D1_GPIO		= 0,
+	GPIO1D1_RESERVED0,
+	GPIO1D1_SDMMC1_PWR,
+	GPIO1D1_RESERVED1,
+	GPIO1D1_I2C5_SDA_M2,
+	GPIO1D1_UART1_RX_M1,
+
+	GPIO1D0_SHIFT		= 0,
+	GPIO1D0_MASK		= GENMASK(2, 0),
+	GPIO1D0_GPIO		= 0,
+	GPIO1D0_I2S2_MCLK_M0,
+	GPIO1D0_SDMMC1_DET,
+	GPIO1D0_SPI1_CS1N_M1,
+	GPIO1D0_I2C5_SCL_M2,
+	GPIO1D0_UART1_TX_M1,
+
+	GPIO2A7_SHIFT		= 12,
+	GPIO2A7_MASK		= GENMASK(14, 12),
+	GPIO2A7_GPIO		= 0,
+	GPIO2A7_LCDC_D3,
+	GPIO2A7_I2S2_SDO_M1,
+	GPIO2A7_RESERVED,
+	GPIO2A7_UART4_RX_M1,
+	GPIO2A7_PWM4_M1,
+	GPIO2A7_SPI0_CS0N_M2,
+
+	GPIO2A6_SHIFT		= 8,
+	GPIO2A6_MASK		= GENMASK(10, 8),
+	GPIO2A6_GPIO		= 0,
+	GPIO2A6_LCDC_D2,
+	GPIO2A6_RGMII_COL_M1,
+	GPIO2A6_CIF_D2_M1,
+	GPIO2A6_UART4_TX_M1,
+	GPIO2A6_PWM5_M1,
+
+	GPIO2A1_SHIFT		= 4,
+	GPIO2A1_MASK		= GENMASK(6, 4),
+	GPIO2A1_GPIO		= 0,
+	GPIO2A1_SPI0_CLK_M1,
+	GPIO2A1_I2S1_SDO_M1,
+	GPIO2A1_UART5_RX_M2,
+
+	GPIO2A0_SHIFT		= 0,
+	GPIO2A0_MASK		= GENMASK(2, 0),
+	GPIO2A0_GPIO		= 0,
+	GPIO2A0_SPI0_CS0N_M1,
+	GPIO2A0_I2S1_SDI_M1,
+	GPIO2A0_UART5_TX_M2,
+
+	GPIO2B1_SHIFT		= 4,
+	GPIO2B1_MASK		= GENMASK(6, 4),
+	GPIO2B1_GPIO		= 0,
+	GPIO2B1_LCDC_D5,
+	GPIO2B1_I2S2_SCLK_M1,
+	GPIO2B1_RESERVED,
+	GPIO2B1_UART5_RX_M1,
+	GPIO2B1_PWM2_M1,
+	GPIO2B1_SPI0_MISO_M2,
+
+	GPIO2B0_SHIFT		= 0,
+	GPIO2B0_MASK		= GENMASK(2, 0),
+	GPIO2B0_GPIO		= 0,
+	GPIO2B0_LCDC_D4,
+	GPIO2B0_I2S2_SDI_M1,
+	GPIO2B0_RESERVED,
+	GPIO2B0_UART5_TX_M1,
+	GPIO2B0_PWM3_IR_M1,
+	GPIO2B0_SPI0_MOSI_M2,
+
+	GPIO3A7_SHIFT		= 12,
+	GPIO3A7_MASK		= GENMASK(14, 12),
+	GPIO3A7_GPIO		= 0,
+	GPIO3A7_CIF_D3_M0,
+	GPIO3A7_RGMII_RXD2_M0,
+	GPIO3A7_I2S0_SDI0_M1,
+	GPIO3A7_UART5_RX_M0,
+	GPIO3A7_CAN_TXD_M1,
+	GPIO3A7_PWM11_IR_M0,
+
+	GPIO3A6_SHIFT		= 8,
+	GPIO3A6_MASK		= GENMASK(10, 8),
+	GPIO3A6_GPIO		= 0,
+	GPIO3A6_CIF_D2_M0,
+	GPIO3A6_RGMII_COL_M0,
+	GPIO3A6_I2S0_SDO0_M1,
+	GPIO3A6_UART5_TX_M0,
+	GPIO3A6_CAN_RXD_M1,
+	GPIO3A6_PWM10_M0,
+
+	GPIO3A5_SHIFT		= 4,
+	GPIO3A5_MASK		= GENMASK(6, 4),
+	GPIO3A5_GPIO		= 0,
+	GPIO3A5_CIF_D1_M0,
+	GPIO3A5_RGMII_CRS_M0,
+	GPIO3A5_I2S0_LRCK_TX_M1,
+	GPIO3A5_UART4_RX_M0,
+	GPIO3A5_I2C3_SDA_M0,
+	GPIO3A5_PWM9_M0,
+
+	GPIO3A4_SHIFT		= 0,
+	GPIO3A4_MASK		= GENMASK(2, 0),
+	GPIO3A4_GPIO		= 0,
+	GPIO3A4_CIF_D0_M0,
+	GPIO3A4_RESERVED,
+	GPIO3A4_I2S0_SCLK_TX_M1,
+	GPIO3A4_UART4_TX_M0,
+	GPIO3A4_I2C3_SCL_M0,
+	GPIO3A4_PWM8_M0,
+
+	GPIO3A3_SHIFT		= 12,
+	GPIO3A3_MASK		= GENMASK(14, 12),
+	GPIO3A3_GPIO		= 0,
+	GPIO3A3_UART2_RX_M1,
+	GPIO3A3_A7_JTAG_TMS_M1,
+
+	GPIO3A2_SHIFT		= 8,
+	GPIO3A2_MASK		= GENMASK(10, 8),
+	GPIO3A2_GPIO		= 0,
+	GPIO3A2_UART2_TX_M1,
+	GPIO3A2_A7_JTAG_TCK_M1,
+
+	GPIO3A1_SHIFT		= 4,
+	GPIO3A1_MASK		= GENMASK(6, 4),
+	GPIO3A1_GPIO		= 0,
+	GPIO3A1_RESERVED0,
+	GPIO3A1_RESERVED1,
+	GPIO3A1_CAN_TXD_M0,
+	GPIO3A1_UART3_RX_M2,
+	GPIO3A1_PWM6_M1,
+	GPIO3A1_RESERVED2,
+	GPIO3A1_I2C4_SDA_M0,
+
+	GPIO3A0_SHIFT		= 0,
+	GPIO3A0_MASK		= GENMASK(2, 0),
+	GPIO3A0_GPIO		= 0,
+	GPIO3A0_RESERVED0,
+	GPIO3A0_RESERVED1,
+	GPIO3A0_CAN_RXD_M0,
+	GPIO3A0_UART3_TX_M2,
+	GPIO3A0_PWM7_IR_M1,
+	GPIO3A0_SPI1_CS1N_M2,
+	GPIO3A0_I2C4_SCL_M0,
+
+	GPIO3C7_SHIFT		= 12,
+	GPIO3C7_MASK		= GENMASK(14, 12),
+	GPIO3C7_GPIO		= 0,
+	GPIO3C7_CIF_HSYNC_M0,
+	GPIO3C7_RGMII_RXCLK_M0,
+	GPIO3C7_RESERVED,
+	GPIO3C7_UART3_RX_M0,
+
+	GPIO3C6_SHIFT		= 8,
+	GPIO3C6_MASK		= GENMASK(10, 0),
+	GPIO3C6_GPIO		= 0,
+	GPIO3C6_CIF_CLKOUT_M0,
+	GPIO3C6_RGMII_TXCLK_M0,
+	GPIO3C6_RESERVED,
+	GPIO3C6_UART3_TX_M0,
+
+	UART2_IO_SEL_SHIFT	= 8,
+	UART2_IO_SEL_MASK	= GENMASK(8, 8),
+	UART2_IO_SEL_M0		= 0,
+	UART2_IO_SEL_M1,
+
+	UART3_IO_SEL_SHIFT	= 10,
+	UART3_IO_SEL_MASK	= GENMASK(11, 10),
+	UART3_IO_SEL_M0		= 0,
+	UART3_IO_SEL_M1,
+	UART3_IO_SEL_M2,
+
+	UART4_IO_SEL_SHIFT	= 12,
+	UART4_IO_SEL_MASK	= GENMASK(13, 12),
+	UART4_IO_SEL_M0		= 0,
+	UART4_IO_SEL_M1,
+	UART4_IO_SEL_M2,
+
+	UART5_IO_SEL_SHIFT	= 14,
+	UART5_IO_SEL_MASK	= GENMASK(15, 14),
+	UART5_IO_SEL_M0		= 0,
+	UART5_IO_SEL_M1,
+	UART5_IO_SEL_M2,
+};
+
+enum {
+	UART1_IO_SEL_SHIFT	= 2,
+	UART1_IO_SEL_MASK	= GENMASK(2, 2),
+	UART1_IO_SEL_M0		= 0,
+	UART1_IO_SEL_M1,
+
+	GPIO0B7_SHIFT		= 12,
+	GPIO0B7_MASK		= GENMASK(14, 12),
+	GPIO0B7_GPIO		= 0,
+	GPIO0B7_RESERVED,
+	GPIO0B7_UART1_RX_M0,
+	GPIO0B7_PWM1_M0,
+
+	GPIO0B6_SHIFT		= 8,
+	GPIO0B6_MASK		= GENMASK(10, 8),
+	GPIO0B6_GPIO		= 0,
+	GPIO0B6_RESERVED,
+	GPIO0B6_UART1_TX_M0,
+	GPIO0B6_PWM0_M0,
+};
+
 void board_debug_uart_init(void)
 {
+#ifdef CONFIG_TPL_BUILD
+	writel(0x03fe0000, PMUGRF_BASE + 0x144);
+	writel((0x7 << (12 + 16)) | (1 << 12), PMUGRF_BASE + 0x8);
+#endif
 
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff560000)
+	static struct rv1126_grf * const grf = (void *)GRF_BASE;
+
+	/* UART0 Switch iomux */
+	rk_clrsetreg(&grf->gpio1c_iomux_l,
+		     GPIO1C3_MASK | GPIO1C2_MASK,
+		     GPIO1C3_UART0_TX << GPIO1C3_SHIFT |
+		     GPIO1C2_UART0_RX << GPIO1C2_SHIFT);
+
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff410000)
+	static struct rv1126_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+    (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+	/* UART1 M0 */
+	rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK,
+		     UART1_IO_SEL_M0 << UART1_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&pmugrf->gpio0b_iomux_h,
+		     GPIO0B7_MASK | GPIO0B6_MASK,
+		     GPIO0B7_UART1_RX_M0 << GPIO0B7_SHIFT |
+		     GPIO0B6_UART1_TX_M0 << GPIO0B6_SHIFT);
+#else
+	/* UART1 M1 */
+	rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK,
+		     UART1_IO_SEL_M1 << UART1_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&topgrf->gpio1d_iomux_l,
+		     GPIO1D1_MASK | GPIO1D0_MASK,
+		     GPIO1D1_UART1_RX_M1 << GPIO1D1_SHIFT |
+		     GPIO1D0_UART1_TX_M1 << GPIO1D0_SHIFT);
+#endif
+
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff570000)
+	static struct rv1126_grf * const grf = (void *)GRF_BASE;
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+    (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+	/* Enable early UART2 channel m0 on the rv1126 */
+	rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK,
+		     UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio1a_iomux_h,
+		     GPIO1A5_MASK | GPIO1A4_MASK,
+		     GPIO1A5_UART2_TX_M0 << GPIO1A5_SHIFT |
+		     GPIO1A4_UART2_RX_M0 << GPIO1A4_SHIFT);
+#else
+	/* Enable early UART2 channel m1 on the rv1126 */
+	rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK,
+		     UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio3a_iomux_l,
+		     GPIO3A3_MASK | GPIO3A2_MASK,
+		     GPIO3A3_UART2_RX_M1 << GPIO3A3_SHIFT |
+		     GPIO3A2_UART2_TX_M1 << GPIO3A2_SHIFT);
+#endif
+
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff580000)
+	static struct rv1126_grf * const grf = (void *)GRF_BASE;
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+    (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+	/* UART3 m0*/
+	rk_clrsetreg(&grf->iofunc_con[2], UART3_IO_SEL_MASK,
+		     UART3_IO_SEL_M0 << UART3_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio3c_iomux_h,
+		     GPIO3C7_MASK | GPIO3C6_MASK,
+		     GPIO3C7_UART3_RX_M0 << GPIO3C7_SHIFT |
+		     GPIO3C6_UART3_TX_M0 << GPIO3C6_SHIFT);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+      (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+	/* UART3 m1*/
+	rk_clrsetreg(&grf->iofunc_con[2], UART3_IO_SEL_MASK,
+		     UART3_IO_SEL_M1 << UART3_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio1a_iomux_h,
+		     GPIO1A7_MASK | GPIO1A6_MASK,
+		     GPIO1A7_UART3_TX_M1 << GPIO1A7_SHIFT |
+		     GPIO1A6_UART3_RX_M1 << GPIO1A6_SHIFT);
+#else
+	/* UART3 m2*/
+	rk_clrsetreg(&grf->iofunc_con[2], UART3_IO_SEL_MASK,
+		     UART3_IO_SEL_M2 << UART3_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio3a_iomux_l,
+		     GPIO3A1_MASK | GPIO3A0_MASK,
+		     GPIO3A1_UART3_RX_M2 << GPIO3A1_SHIFT |
+		     GPIO3A0_UART3_TX_M2 << GPIO3A0_SHIFT);
+#endif
+
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff590000)
+	static struct rv1126_grf * const grf = (void *)GRF_BASE;
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+    (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+	/* UART4 m0*/
+	rk_clrsetreg(&grf->iofunc_con[2], UART4_IO_SEL_MASK,
+		     UART4_IO_SEL_M0 << UART4_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio3a_iomux_h,
+		     GPIO3A5_MASK | GPIO3A4_MASK,
+		     GPIO3A5_UART4_RX_M0 << GPIO3A5_SHIFT |
+		     GPIO3A4_UART4_TX_M0 << GPIO3A4_SHIFT);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+      (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+	/* UART4 m1*/
+	rk_clrsetreg(&grf->iofunc_con[2], UART4_IO_SEL_MASK,
+		     UART4_IO_SEL_M1 << UART4_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio2a_iomux_h,
+		     GPIO2A7_MASK | GPIO2A6_MASK,
+		     GPIO2A7_UART4_RX_M1 << GPIO2A7_SHIFT |
+		     GPIO2A6_UART4_TX_M1 << GPIO2A6_SHIFT);
+#else
+	/* UART4 m2*/
+	rk_clrsetreg(&grf->iofunc_con[2], UART4_IO_SEL_MASK,
+		     UART4_IO_SEL_M2 << UART4_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio1d_iomux_h,
+		     GPIO1D5_MASK | GPIO1D4_MASK,
+		     GPIO1D5_UART4_TX_M2 << GPIO1D5_SHIFT |
+		     GPIO1D4_UART4_RX_M2 << GPIO1D4_SHIFT);
+#endif
+
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff5a0000)
+	static struct rv1126_grf * const grf = (void *)GRF_BASE;
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+    (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+	/* UART5 m0*/
+	rk_clrsetreg(&grf->iofunc_con[2], UART5_IO_SEL_MASK,
+		     UART5_IO_SEL_M0 << UART5_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio3a_iomux_h,
+		     GPIO3A7_MASK | GPIO3A6_MASK,
+		     GPIO3A7_UART5_RX_M0 << GPIO3A7_SHIFT |
+		     GPIO3A6_UART5_TX_M0 << GPIO3A6_SHIFT);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+      (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+	/* UART5 m1*/
+	rk_clrsetreg(&grf->iofunc_con[2], UART5_IO_SEL_MASK,
+		     UART5_IO_SEL_M1 << UART5_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio2b_iomux_l,
+		     GPIO2B1_MASK | GPIO2B0_MASK,
+		     GPIO2B1_UART5_RX_M1 << GPIO2B1_SHIFT |
+		     GPIO2B0_UART5_TX_M1 << GPIO2B0_SHIFT);
+#else
+	/* UART5 m2*/
+	rk_clrsetreg(&grf->iofunc_con[2], UART5_IO_SEL_MASK,
+		     UART5_IO_SEL_M2 << UART5_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&grf->gpio2a_iomux_l,
+		     GPIO2A1_MASK | GPIO2A0_MASK,
+		     GPIO2A1_UART5_RX_M2 << GPIO2A1_SHIFT |
+		     GPIO2A0_UART5_TX_M2 << GPIO2A0_SHIFT);
+#endif
+#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
 }
 
 int arch_cpu_init(void)