rockchip: rk356x: setting ebc priority to 0x3
Enable all power domain except npu and gpu. Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: I3757b8770b6d5a2a96b9d0945bbe536b6d387741
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@ -39,6 +39,14 @@ DECLARE_GLOBAL_DATA_PTR;
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#define CPU_GRF_BASE 0xfdc30000
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#define GRF_CORE_PVTPLL_CON0 (0x10)
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#define PMU_PWR_GATE_SFTCON (0xA0)
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#define PMU_PWR_DWN_ST (0x98)
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#define PMU_BUS_IDLE_SFTCON0 (0x50)
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#define PMU_BUS_IDLE_ST (0x68)
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#define PMU_BUS_IDLE_ACK (0x60)
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#define EBC_PRIORITY_REG (0xfe158008)
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enum {
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/* PMU_GRF_GPIO0C_IOMUX_L */
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GPIO0C1_SHIFT = 4,
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@ -730,6 +738,54 @@ void board_debug_uart_init(void)
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#endif
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}
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#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
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static void qos_priority_init(void)
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{
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u32 delay;
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/* enable all pd except npu and gpu */
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writel(0xffff0000 & ~(BIT(0 + 16) | BIT(1 + 16)),
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PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
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delay = 1000;
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do {
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udelay(1);
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delay--;
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if (delay == 0) {
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printf("Fail to set domain.");
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hang();
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}
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} while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & ~(BIT(0) | BIT(1)));
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/* release all idle request except npu and gpu */
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writel(0xffff0000 & ~(BIT(1 + 16) | BIT(2 + 16)),
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PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON0);
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delay = 1000;
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/* wait ack status */
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do {
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udelay(1);
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delay--;
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if (delay == 0) {
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printf("Fail to get ack on domain.\n");
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hang();
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}
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} while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK) & ~(BIT(1) | BIT(2)));
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delay = 1000;
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/* wait idle status */
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do {
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udelay(1);
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delay--;
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if (delay == 0) {
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printf("Fail to set idle on domain.\n");
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hang();
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}
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} while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST) & ~(BIT(1) | BIT(2)));
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writel(0x303, EBC_PRIORITY_REG);
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}
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#endif
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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@ -765,6 +821,10 @@ int arch_cpu_init(void)
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/* Set core pvtpll ring length */
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writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
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#ifndef CONFIG_TPL_BUILD
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qos_priority_init();
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#endif
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#endif
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return 0;
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