mtd: nand: add the rockchip nand controller driver
Add basic Rockchip nand driver. Driver in current state has 16, 24, 40, 60 per 1024B BCH/ECC ability and 8 bit asynchronous flash interface support. Other features will come later. Change-Id: I8e766afe7358a2357d75cfe094c4cd6fe92bd281 Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Paweł Jarosz
Kever Yang
parent
037e961371
commit
a3584243c9
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@ -76,6 +76,12 @@ config NAND_PXA3XX
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This enables the driver for the NAND flash device found on
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PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
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config NAND_ROCKCHIP
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bool "Support for NAND on Rockchip SoCs"
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select SYS_NAND_SELF_INIT
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---help---
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Enable support for Rockchip nand.
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config NAND_SUNXI
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bool "Support for NAND on Allwinner SoCs"
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depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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@ -66,6 +66,7 @@ obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
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obj-$(CONFIG_NAND_PLAT) += nand_plat.o
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obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
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obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
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obj-$(CONFIG_NAND_ROCKCHIP) += rockchip_nand.o
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else # minimal SPL drivers
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@ -0,0 +1,660 @@
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/*
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* Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com>
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* Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <inttypes.h>
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#include <nand.h>
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#include <linux/kernel.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define NANDC_V6_BOOTROM_ECC 24
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#define NANDC_V6_NUM_BANKS 8
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#define NANDC_V6_DEF_TIMEOUT 20000
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#define NANDC_V6_READ 0
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#define NANDC_V6_WRITE 1
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#define NANDC_REG_V6_FMCTL 0x00
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#define NANDC_REG_V6_FMWAIT 0x04
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#define NANDC_REG_V6_FLCTL 0x08
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#define NANDC_REG_V6_BCHCTL 0x0c
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#define NANDC_REG_V6_DMA_CFG 0x10
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#define NANDC_REG_V6_DMA_BUF0 0x14
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#define NANDC_REG_V6_DMA_BUF1 0x18
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#define NANDC_REG_V6_DMA_ST 0x1C
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#define NANDC_REG_V6_BCHST 0x20
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#define NANDC_REG_V6_RANDMZ 0x150
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#define NANDC_REG_V6_VER 0x160
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#define NANDC_REG_V6_INTEN 0x16C
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#define NANDC_REG_V6_INTCLR 0x170
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#define NANDC_REG_V6_INTST 0x174
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#define NANDC_REG_V6_SPARE0 0x200
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#define NANDC_REG_V6_SPARE1 0x230
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#define NANDC_REG_V6_BANK0 0x800
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#define NANDC_REG_V6_SRAM0 0x1000
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#define NANDC_REG_V6_SRAM_SIZE 0x400
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#define NANDC_REG_V6_DATA 0x00
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#define NANDC_REG_V6_ADDR 0x04
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#define NANDC_REG_V6_CMD 0x08
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/* FMCTL */
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#define NANDC_V6_FM_WP BIT(8)
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#define NANDC_V6_FM_CE_SEL_M 0xFF
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#define NANDC_V6_FM_CE_SEL(x) (1 << (x))
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#define NANDC_V6_FM_FREADY BIT(9)
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/* FLCTL */
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#define NANDC_V6_FL_RST BIT(0)
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#define NANDC_V6_FL_DIR_S 0x1
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#define NANDC_V6_FL_XFER_START BIT(2)
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#define NANDC_V6_FL_XFER_EN BIT(3)
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#define NANDC_V6_FL_ST_BUF_S 0x4
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#define NANDC_V6_FL_XFER_COUNT BIT(5)
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#define NANDC_V6_FL_ACORRECT BIT(10)
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#define NANDC_V6_FL_XFER_READY BIT(20)
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/* BCHCTL */
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#define NAND_V6_BCH_REGION_S 0x5
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#define NAND_V6_BCH_REGION_M 0x7
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/* BCHST */
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#define NANDC_V6_BCH0_ST_ERR BIT(2)
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#define NANDC_V6_BCH1_ST_ERR BIT(15)
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#define NANDC_V6_ECC_ERR_CNT0(x) ((((x & (0x1F << 3)) >> 3) \
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| ((x & (1 << 27)) >> 22)) & 0x3F)
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#define NANDC_V6_ECC_ERR_CNT1(x) ((((x & (0x1F << 16)) >> 16) \
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| ((x & (1 << 29)) >> 24)) & 0x3F)
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struct rk_nand {
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uint32_t banks[NANDC_V6_NUM_BANKS];
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struct nand_hw_control controller;
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uint32_t ecc_strength;
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struct mtd_info mtd;
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bool bootromblocks;
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void __iomem *regs;
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int selected_bank;
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};
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static struct nand_ecclayout nand_oob_fix = {
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.eccbytes = 24,
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.eccpos = {
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4, 5, 6, 7, 8, 9, 10},
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.oobfree = {
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{.offset = 0,
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.length = 4} }
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};
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static inline struct rk_nand *to_rknand(struct nand_hw_control *ctrl)
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{
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return container_of(ctrl, struct rk_nand, controller);
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}
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static void rockchip_nand_init(struct rk_nand *rknand)
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{
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writel(0, rknand->regs + NANDC_REG_V6_RANDMZ);
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writel(0, rknand->regs + NANDC_REG_V6_DMA_CFG);
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writel(0, rknand->regs + NANDC_REG_V6_BCHCTL);
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writel(NANDC_V6_FM_WP, rknand->regs + NANDC_REG_V6_FMCTL);
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writel(0x1081, rknand->regs + NANDC_REG_V6_FMWAIT);
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}
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static void rockchip_nand_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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void __iomem *bank_base;
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uint32_t reg;
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int banknr;
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reg = readl(rknand->regs + NANDC_REG_V6_FMCTL);
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reg &= ~NANDC_V6_FM_CE_SEL_M;
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if (chipnr == -1) {
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banknr = -1;
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} else {
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banknr = rknand->banks[chipnr];
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bank_base = rknand->regs + NANDC_REG_V6_BANK0 + banknr * 0x100;
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chip->IO_ADDR_R = bank_base;
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chip->IO_ADDR_W = bank_base;
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reg |= 1 << banknr;
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}
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writel(reg, rknand->regs + NANDC_REG_V6_FMCTL);
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rknand->selected_bank = banknr;
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}
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static void rockchip_nand_cmd_ctrl(struct mtd_info *mtd,
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int dat,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0
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+ rknand->selected_bank * 0x100;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_ALE)
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bank_base += NANDC_REG_V6_ADDR;
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else if (ctrl & NAND_CLE)
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bank_base += NANDC_REG_V6_CMD;
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chip->IO_ADDR_W = bank_base;
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}
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if (dat != NAND_CMD_NONE)
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writeb(dat & 0xFF, chip->IO_ADDR_W);
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}
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static void rockchip_nand_read_buf(struct mtd_info *mtd,
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uint8_t *buf,
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int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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int offs = 0;
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void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0
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+ rknand->selected_bank * 0x100;
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for (offs = 0; offs < len; offs++)
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buf[offs] = readb(bank_base);
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}
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static void rockchip_nand_write_buf(struct mtd_info *mtd,
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const uint8_t *buf,
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int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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int offs = 0;
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void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0
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+ rknand->selected_bank * 0x100;
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for (offs = 0; offs < len; offs++)
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writeb(buf[offs], bank_base);
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}
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static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd)
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{
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uint8_t ret;
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rockchip_nand_read_buf(mtd, &ret, 1);
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return ret;
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}
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static int rockchip_nand_dev_ready(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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if (readl(rknand->regs + NANDC_REG_V6_FMCTL) & NANDC_V6_FM_FREADY)
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return 1;
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return 0;
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}
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static int rockchip_nand_hw_ecc_setup(struct mtd_info *mtd,
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struct nand_ecc_ctrl *ecc,
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uint32_t strength)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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u32 reg;
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ecc->strength = strength;
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ecc->bytes = DIV_ROUND_UP(ecc->strength * 14, 8);
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ecc->bytes = ALIGN(ecc->bytes, 2);
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switch (ecc->strength) {
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case 60:
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reg = 0x00040010;
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break;
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case 40:
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reg = 0x00040000;
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break;
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case 24:
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reg = 0x00000010;
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break;
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case 16:
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reg = 0x00000000;
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break;
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default:
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return -EINVAL;
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}
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writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL);
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return 0;
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}
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static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand,
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u8 dir,
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u8 st_buf)
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{
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u32 reg;
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reg = readl(rknand->regs + NANDC_REG_V6_BCHCTL);
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reg = (reg & (~(NAND_V6_BCH_REGION_M << NAND_V6_BCH_REGION_S))) |
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(rknand->selected_bank << NAND_V6_BCH_REGION_S);
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writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL);
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reg = (dir << NANDC_V6_FL_DIR_S) | (st_buf << NANDC_V6_FL_ST_BUF_S) |
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NANDC_V6_FL_XFER_EN | NANDC_V6_FL_XFER_COUNT |
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NANDC_V6_FL_ACORRECT;
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writel(reg, rknand->regs + NANDC_REG_V6_FLCTL);
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reg |= NANDC_V6_FL_XFER_START;
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writel(reg, rknand->regs + NANDC_REG_V6_FLCTL);
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}
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static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand)
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{
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int timeout = NANDC_V6_DEF_TIMEOUT;
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int reg;
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while (timeout--) {
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reg = readl(rknand->regs + NANDC_REG_V6_FLCTL);
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if ((reg & NANDC_V6_FL_XFER_READY) != 0)
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break;
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udelay(1);
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}
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if (timeout == 0)
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return -1;
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return 0;
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}
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static void rockchip_nand_read_extra_oob(struct mtd_info *mtd, u8 *oob)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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int offset = ((ecc->bytes + ecc->prepad) * ecc->steps);
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int len = mtd->oobsize - offset;
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if (len <= 0)
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return;
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chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset + mtd->writesize, -1);
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rockchip_nand_read_buf(mtd, oob + offset, len);
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}
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static void rockchip_nand_write_extra_oob(struct mtd_info *mtd, u8 *oob)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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int offset = ((ecc->bytes + ecc->prepad) * ecc->steps);
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int len = mtd->oobsize - offset;
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if (len <= 0)
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return;
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chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset + mtd->writesize, -1);
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rockchip_nand_write_buf(mtd, oob + offset, len);
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}
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static int rockchip_nand_hw_syndrome_pio_read_page(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint8_t *buf,
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int oob_required,
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int page)
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{
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struct rk_nand *rknand = to_rknand(chip->controller);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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void __iomem *sram_base = rknand->regs + NANDC_REG_V6_SRAM0;
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unsigned int max_bitflips = 0;
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int ret, step, bch_st;
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int offset = page * mtd->writesize;
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if (rknand->bootromblocks && (offset < (7 * mtd->erasesize)))
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rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V6_BOOTROM_ECC);
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rockchip_nand_pio_xfer_start(rknand, NANDC_V6_READ, 0);
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for (step = 0; step < ecc->steps; step++) {
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int data_off = step * ecc->size;
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int oob_off = step * (ecc->bytes + ecc->prepad);
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u8 *data = buf + data_off;
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u8 *oob = chip->oob_poi + oob_off;
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ret = rockchip_nand_wait_pio_xfer_done(rknand);
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if (ret)
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return ret;
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bch_st = readl(rknand->regs + NANDC_REG_V6_BCHST);
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if (bch_st & NANDC_V6_BCH0_ST_ERR) {
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mtd->ecc_stats.failed++;
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max_bitflips = -1;
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} else {
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ret = NANDC_V6_ECC_ERR_CNT0(bch_st);
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mtd->ecc_stats.corrected += ret;
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max_bitflips = max_t(unsigned int, max_bitflips, ret);
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}
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if ((step + 1) < ecc->steps)
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rockchip_nand_pio_xfer_start(rknand, NANDC_V6_READ,
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(step + 1) & 0x1);
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memcpy_fromio(data, sram_base + NANDC_REG_V6_SRAM_SIZE *
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(step & 1), ecc->size);
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if (step & 1)
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memcpy_fromio(oob, rknand->regs + NANDC_REG_V6_SPARE1, 4);
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else
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memcpy_fromio(oob, rknand->regs + NANDC_REG_V6_SPARE0, 4);
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}
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rockchip_nand_read_extra_oob(mtd, chip->oob_poi);
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if (rknand->bootromblocks)
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rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength);
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return max_bitflips;
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}
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static uint32_t rockchip_nand_make_bootrom_compat(struct mtd_info *mtd,
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int page,
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const u8 *oob,
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bool bootromblocks)
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{
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int pages_per_block = mtd->erasesize / mtd->writesize;
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int offset = page * mtd->writesize;
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if ((offset < (2 * mtd->erasesize)) || !(page % 2) ||
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(offset >= (7 * mtd->erasesize)) || !bootromblocks)
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return oob[3] | (oob[2] << 8) | (oob[1] << 16) | (oob[0] << 24);
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return (page % pages_per_block + 1) * 4;
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}
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static int rockchip_nand_hw_syndrome_pio_write_page(struct mtd_info *mtd,
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struct nand_chip *chip,
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const uint8_t *buf,
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int oob_required,
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int page)
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{
|
||||
struct rk_nand *rknand = to_rknand(chip->controller);
|
||||
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
||||
void __iomem *sram_base = rknand->regs + NANDC_REG_V6_SRAM0;
|
||||
int ret, index, step = 0;
|
||||
int offset = page * mtd->writesize;
|
||||
int data_off = step * ecc->size;
|
||||
int oob_off = step * (ecc->bytes + ecc->prepad);
|
||||
const u8 *data = buf + data_off;
|
||||
const u8 *oob = chip->oob_poi + oob_off;
|
||||
|
||||
if (rknand->bootromblocks && (offset < (7 * mtd->erasesize)))
|
||||
rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V6_BOOTROM_ECC);
|
||||
|
||||
index = rockchip_nand_make_bootrom_compat(mtd, page, oob,
|
||||
rknand->bootromblocks);
|
||||
|
||||
memcpy_toio(sram_base, data, ecc->size);
|
||||
memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE0, &index, ecc->prepad);
|
||||
|
||||
for (step = 1; step <= ecc->steps; step++) {
|
||||
rockchip_nand_pio_xfer_start(rknand, NANDC_V6_WRITE,
|
||||
(step - 1) & 0x1);
|
||||
|
||||
data_off = step * ecc->size;
|
||||
oob_off = step * (ecc->bytes + ecc->prepad);
|
||||
data = buf + data_off;
|
||||
oob = chip->oob_poi + oob_off;
|
||||
|
||||
if (step < ecc->steps) {
|
||||
memcpy_toio(sram_base + NANDC_REG_V6_SRAM_SIZE *
|
||||
(step & 1), data, ecc->size);
|
||||
if (step & 1)
|
||||
memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE1,
|
||||
oob, ecc->prepad);
|
||||
else
|
||||
memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE0,
|
||||
oob, ecc->prepad);
|
||||
}
|
||||
|
||||
ret = rockchip_nand_wait_pio_xfer_done(rknand);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
rockchip_nand_write_extra_oob(mtd, chip->oob_poi);
|
||||
|
||||
rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const u8 strengths[] = {60, 40, 24, 16};
|
||||
|
||||
static int rockchip_nand_ecc_max_strength(struct mtd_info *mtd,
|
||||
struct nand_ecc_ctrl *ecc)
|
||||
{
|
||||
uint32_t max_strength, index;
|
||||
|
||||
max_strength = ((mtd->oobsize / ecc->steps) - ecc->prepad) * 8 / 14;
|
||||
|
||||
for (index = 0; index < ARRAY_SIZE(strengths); index++)
|
||||
if (max_strength >= strengths[index])
|
||||
break;
|
||||
|
||||
if (index >= ARRAY_SIZE(strengths))
|
||||
return -ENOTSUPP;
|
||||
|
||||
return strengths[index];
|
||||
}
|
||||
|
||||
static bool rockchip_nand_strength_is_valid(int strength)
|
||||
{
|
||||
uint32_t index;
|
||||
|
||||
for (index = 0; index < ARRAY_SIZE(strengths); index++)
|
||||
if (strength == strengths[index])
|
||||
break;
|
||||
|
||||
if (index == ARRAY_SIZE(strengths))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int rockchip_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
|
||||
struct nand_ecc_ctrl *ecc)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct rk_nand *rknand = to_rknand(chip->controller);
|
||||
uint32_t strength;
|
||||
int index;
|
||||
|
||||
ecc->prepad = 4;
|
||||
ecc->steps = mtd->writesize / ecc->size;
|
||||
|
||||
if (fdtdec_get_bool(gd->fdt_blob, chip->flash_node,
|
||||
"rockchip,protect-bootrom-blocks"))
|
||||
rknand->bootromblocks = true;
|
||||
else
|
||||
rknand->bootromblocks = false;
|
||||
|
||||
if (rockchip_nand_strength_is_valid(ecc->strength))
|
||||
strength = ecc->strength;
|
||||
else
|
||||
strength = rockchip_nand_ecc_max_strength(mtd, ecc);
|
||||
|
||||
rockchip_nand_hw_ecc_setup(mtd, ecc, strength);
|
||||
|
||||
rknand->ecc_strength = ecc->strength;
|
||||
|
||||
nand_oob_fix.eccbytes = ecc->bytes * ecc->steps;
|
||||
for (index = 0; index < ecc->bytes; index++)
|
||||
nand_oob_fix.eccpos[index] = index + ecc->prepad;
|
||||
ecc->layout = &nand_oob_fix;
|
||||
|
||||
if (mtd->oobsize < ((ecc->bytes + ecc->prepad) * ecc->steps)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_nand_ecc_init(struct mtd_info *mtd,
|
||||
struct nand_ecc_ctrl *ecc)
|
||||
{
|
||||
int ret;
|
||||
|
||||
switch (ecc->mode) {
|
||||
case NAND_ECC_HW_SYNDROME:
|
||||
ret = rockchip_nand_hw_ecc_ctrl_init(mtd, ecc);
|
||||
if (ret)
|
||||
return ret;
|
||||
ecc->read_page = rockchip_nand_hw_syndrome_pio_read_page;
|
||||
ecc->write_page = rockchip_nand_hw_syndrome_pio_write_page;
|
||||
break;
|
||||
case NAND_ECC_SOFT_BCH:
|
||||
case NAND_ECC_NONE:
|
||||
case NAND_ECC_SOFT:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_nand_chip_init(int node, struct rk_nand *rknand, int devnum)
|
||||
{
|
||||
const void *blob = gd->fdt_blob;
|
||||
struct nand_chip *chip;
|
||||
struct mtd_info *mtd;
|
||||
int ret;
|
||||
|
||||
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
|
||||
|
||||
chip->chip_delay = 50;
|
||||
chip->flash_node = node;
|
||||
chip->select_chip = rockchip_nand_select_chip;
|
||||
chip->cmd_ctrl = rockchip_nand_cmd_ctrl;
|
||||
chip->read_buf = rockchip_nand_read_buf;
|
||||
chip->write_buf = rockchip_nand_write_buf;
|
||||
chip->read_byte = rockchip_nand_read_byte;
|
||||
chip->dev_ready = rockchip_nand_dev_ready;
|
||||
chip->controller = &rknand->controller;
|
||||
|
||||
rknand->banks[devnum] = fdtdec_get_int(blob, node, "reg", -1);
|
||||
|
||||
if (rknand->banks[devnum] < 0)
|
||||
return -EINVAL;
|
||||
|
||||
mtd = nand_to_mtd(chip);
|
||||
mtd->name = "rknand";
|
||||
|
||||
ret = nand_scan_ident(mtd, 1, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = rockchip_nand_ecc_init(mtd, &chip->ecc);
|
||||
if (ret) {
|
||||
debug("rockchip_nand_ecc_init failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = nand_scan_tail(mtd);
|
||||
if (ret) {
|
||||
debug("nand_scan_tail failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = nand_register(devnum, mtd);
|
||||
if (ret) {
|
||||
debug("Failed to register mtd device: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_nand_chips_init(int node, struct rk_nand *rknand)
|
||||
{
|
||||
const void *blob = gd->fdt_blob;
|
||||
int nand_node;
|
||||
int ret, i = 0;
|
||||
|
||||
for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
|
||||
nand_node = fdt_next_subnode(blob, nand_node)) {
|
||||
ret = rockchip_nand_chip_init(nand_node, rknand, i++);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_nand_init(void)
|
||||
{
|
||||
const void *blob = gd->fdt_blob;
|
||||
struct rk_nand *rknand;
|
||||
fdt_addr_t regs;
|
||||
int node;
|
||||
int ret;
|
||||
|
||||
rknand = kzalloc(sizeof(*rknand), GFP_KERNEL);
|
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC);
|
||||
|
||||
if (node < 0) {
|
||||
debug("Nand node not found\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (!fdtdec_get_is_enabled(blob, node)) {
|
||||
debug("Nand disabled in device tree\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
regs = fdtdec_get_addr(blob, node, "reg");
|
||||
if (regs == FDT_ADDR_T_NONE) {
|
||||
debug("Nand address not found\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
rknand->regs = (void *)regs;
|
||||
|
||||
spin_lock_init(&rknand->controller.lock);
|
||||
init_waitqueue_head(&rknand->controller.wq);
|
||||
|
||||
rockchip_nand_init(rknand);
|
||||
|
||||
ret = rockchip_nand_chips_init(node, rknand);
|
||||
if (ret) {
|
||||
debug("Failed to init nand chips\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
return;
|
||||
err:
|
||||
kfree(rknand);
|
||||
}
|
||||
|
||||
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
|
||||
{
|
||||
struct mtd_info *mtd;
|
||||
|
||||
mtd = get_nand_dev_by_index(0);
|
||||
return nand_read_skip_bad(mtd, offs, &size, NULL, size, (u_char *)dst);
|
||||
}
|
||||
|
||||
void nand_deselect(void) {}
|
||||
|
|
@ -159,6 +159,7 @@ enum fdt_compat_id {
|
|||
COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */
|
||||
COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */
|
||||
COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */
|
||||
COMPAT_ROCKCHIP_NANDC, /* Rockchip NAND controller */
|
||||
|
||||
COMPAT_COUNT,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -70,6 +70,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
|
|||
COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
|
||||
COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
|
||||
COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
|
||||
COMPAT(ROCKCHIP_NANDC, "rockchip,nandc"),
|
||||
};
|
||||
|
||||
const char *fdtdec_get_compatible(enum fdt_compat_id id)
|
||||
|
|
|
|||
Loading…
Reference in New Issue