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video/drm: analogix_dp: Move PLL lock check to analogix_dp_set_link_bandwidth() 

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Iffd2ff42de9102cf0293cf7bb68422dd6331474b
This commit is contained in:
Wyon Bi 2020-12-10 02:44:24 +00:00
parent 253c2dc8a6
commit a6285d17cb
2 changed files with 13 additions and 28 deletions
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14
drivers/video/drm/analogix_dp.c
View File

@ -84,7 +84,7 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
static int analogix_dp_link_start(struct analogix_dp_device *dp) static int analogix_dp_link_start(struct analogix_dp_device *dp)
{ {
u8 buf[4]; u8 buf[4];
int lane, lane_count, pll_tries, retval; int lane, lane_count, retval;
lane_count = dp->link_train.lane_count; lane_count = dp->link_train.lane_count;
@ -112,18 +112,6 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
DP_TRAIN_PRE_EMPH_LEVEL_0; DP_TRAIN_PRE_EMPH_LEVEL_0;
analogix_dp_set_lane_link_training(dp); analogix_dp_set_lane_link_training(dp);
/* Wait for PLL lock */
pll_tries = 0;
while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Wait for PLL lock timed out\n");
return -ETIMEDOUT;
}
pll_tries++;
udelay(120);
}
/* Set training pattern 1 */ /* Set training pattern 1 */
analogix_dp_set_training_pattern(dp, TRAINING_PTN1); analogix_dp_set_training_pattern(dp, TRAINING_PTN1);

27
drivers/video/drm/analogix_dp_reg.c
View File

@ -21,6 +21,7 @@
#include <syscon.h> #include <syscon.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#include <linux/iopoll.h>
#include "rockchip_display.h" #include "rockchip_display.h"
#include "rockchip_crtc.h" #include "rockchip_crtc.h"
@ -357,7 +358,6 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
void analogix_dp_init_analog_func(struct analogix_dp_device *dp) void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
{ {
u32 reg; u32 reg;
int timeout_loop = 0;
analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
@ -369,19 +369,7 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg); analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg);
/* Power up PLL */ /* Power up PLL */
if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { analogix_dp_set_pll_power_down(dp, 0);
analogix_dp_set_pll_power_down(dp, 0);
while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
timeout_loop++;
if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev,
"failed to get pll lock status\n");
return;
}
udelay(20);
}
}
/* Enable Serdes FIFO function and Link symbol clock domain module */ /* Enable Serdes FIFO function and Link symbol clock domain module */
reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2);
@ -920,11 +908,20 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
{ {
u32 reg; u32 reg, status;
int ret;
reg = bwtype; reg = bwtype;
if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg); analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg);
ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
status != PLL_UNLOCKED,
120 * DP_TIMEOUT_LOOP_COUNT);
if (ret) {
dev_err(dp->dev, "Wait for pll lock failed %d\n", ret);
return;
}
} }
void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)