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rockchip: tpl: add arch_cpu_init() 

The arch_cpu_init() should be called for cpu early init
for tpl.

Change-Id: I3aad0f284089d8523710a2d24daab44995fa148d
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
This commit is contained in:
Zhihuan He 2020-09-25 10:02:32 +08:00 committed by Jianhong Chen
parent 7329ce5782
commit ad11931911
7 changed files with 85 additions and 68 deletions
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2
arch/arm/mach-rockchip/rk322x/rk322x.c
View File

@ -17,6 +17,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_SD] = "/dwmmc@30000000",
};
#ifndef CONFIG_TPL_BUILD
int arch_cpu_init(void)
{
static struct rk322x_grf * const grf = (void *)GRF_BASE;
@ -49,6 +50,7 @@ int arch_cpu_init(void)
return 0;
}
#endif
void board_debug_uart_init(void)
{

3
arch/arm/mach-rockchip/rk3288/rk3288.c
View File

@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
};
#ifndef CONFIG_TPL_BUILD
#ifdef CONFIG_SPL_BUILD
static void configure_l2ctlr(void)
{
@ -87,9 +88,9 @@ int arch_cpu_init(void)
writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2), VIO0_VOP_QOS_BASE);
writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2), VIO1_VOP_QOS_BASE);
#endif
return 0;
}
#endif
void board_debug_uart_init(void)
{

3
arch/arm/mach-rockchip/rk3328/rk3328.c
View File

@ -47,6 +47,8 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000",
[BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000",
};
#ifndef CONFIG_TPL_BUILD
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
@ -66,6 +68,7 @@ int arch_cpu_init(void)
#endif
return 0;
}
#endif
void board_debug_uart_init(void)
{

134
arch/arm/mach-rockchip/rk3368/rk3368.c
View File

@ -124,6 +124,73 @@ int arch_early_init_r(void)
}
#endif
void board_debug_uart_init(void)
{
/*
* N.B.: This is called before the device-model has been
* initialised. For this reason, we can not access
* the GRF address range using the syscon API.
*/
struct rk3368_grf * const grf __maybe_unused =
(struct rk3368_grf * const)0xff770000;
enum {
/* UART0 */
GPIO2D1_MASK = GENMASK(3, 2),
GPIO2D1_GPIO = 0,
GPIO2D1_UART0_SOUT = (1 << 2),
GPIO2D0_MASK = GENMASK(1, 0),
GPIO2D0_GPIO = 0,
GPIO2D0_UART0_SIN = (1 << 0),
/* UART2 */
GPIO2A6_MASK = GENMASK(13, 12),
GPIO2A6_GPIO = 0,
GPIO2A6_UART0_SIN = (1 << 13),
GPIO2A6_UART2_SIN = (2 << 12),
GPIO2A5_MASK = GENMASK(11, 10),
GPIO2A5_GPIO = 0,
GPIO2A5_UART0_SOUT = (1 << 11),
GPIO2A5_UART2_SOUT = (2 << 10),
};
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
/* Enable early UART0 on the RK3368 */
rk_clrsetreg(&grf->gpio2d_iomux,
GPIO2D0_MASK, GPIO2D0_UART0_SIN);
rk_clrsetreg(&grf->gpio2d_iomux,
GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
struct rk3368_pmu_grf * const pmugrf __maybe_unused =
(struct rk3368_pmu_grf * const)0xff738000;
enum {
/* UART4 */
GPIO0D2_MASK = GENMASK(5, 4),
GPIO0D2_GPIO = 0,
GPIO0D2_UART4_SOUT = (3 << 4),
GPIO0D3_MASK = GENMASK(7, 6),
GPIO0D3_GPIO = 0,
GPIO0D3_UART4_SIN = (3 << 6),
};
/* Enable early UART4 on the PX5 */
rk_clrsetreg(&pmugrf->gpio0d_iomux,
GPIO0D2_MASK | GPIO0D3_MASK,
GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
/* Enable early UART2 on the RK3368 */
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A6_MASK, GPIO2A6_UART2_SIN);
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
#endif
}
#ifndef CONFIG_TPL_BUILD
static void cpu_axi_qos_prority_level_config(void)
{
u32 level;
@ -218,72 +285,6 @@ static void sgrf_init(void)
}
#endif
void board_debug_uart_init(void)
{
/*
* N.B.: This is called before the device-model has been
* initialised. For this reason, we can not access
* the GRF address range using the syscon API.
*/
struct rk3368_grf * const grf __maybe_unused =
(struct rk3368_grf * const)0xff770000;
enum {
/* UART0 */
GPIO2D1_MASK = GENMASK(3, 2),
GPIO2D1_GPIO = 0,
GPIO2D1_UART0_SOUT = (1 << 2),
GPIO2D0_MASK = GENMASK(1, 0),
GPIO2D0_GPIO = 0,
GPIO2D0_UART0_SIN = (1 << 0),
/* UART2 */
GPIO2A6_MASK = GENMASK(13, 12),
GPIO2A6_GPIO = 0,
GPIO2A6_UART0_SIN = (1 << 13),
GPIO2A6_UART2_SIN = (2 << 12),
GPIO2A5_MASK = GENMASK(11, 10),
GPIO2A5_GPIO = 0,
GPIO2A5_UART0_SOUT = (1 << 11),
GPIO2A5_UART2_SOUT = (2 << 10),
};
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
/* Enable early UART0 on the RK3368 */
rk_clrsetreg(&grf->gpio2d_iomux,
GPIO2D0_MASK, GPIO2D0_UART0_SIN);
rk_clrsetreg(&grf->gpio2d_iomux,
GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
struct rk3368_pmu_grf * const pmugrf __maybe_unused =
(struct rk3368_pmu_grf * const)0xff738000;
enum {
/* UART4 */
GPIO0D2_MASK = GENMASK(5, 4),
GPIO0D2_GPIO = 0,
GPIO0D2_UART4_SOUT = (3 << 4),
GPIO0D3_MASK = GENMASK(7, 6),
GPIO0D3_GPIO = 0,
GPIO0D3_UART4_SIN = (3 << 6),
};
/* Enable early UART4 on the PX5 */
rk_clrsetreg(&pmugrf->gpio0d_iomux,
GPIO0D2_MASK | GPIO0D3_MASK,
GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
/* Enable early UART2 on the RK3368 */
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A6_MASK, GPIO2A6_UART2_SIN);
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
#endif
}
int arch_cpu_init(void)
{
/* DDR read latency config */
@ -308,3 +309,4 @@ int arch_cpu_init(void)
return 0;
}
#endif

2
arch/arm/mach-rockchip/rk3399/rk3399.c
View File

@ -76,6 +76,7 @@ void rockchip_stimer_init(void)
#define NIU_PERILP_NSP_ADDR 0xffad8188
#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
#ifndef CONFIG_TPL_BUILD
int arch_cpu_init(void)
{
struct rk3399_pmugrf_regs *pmugrf = (void *)PMUGRF_BASE;
@ -118,6 +119,7 @@ int arch_cpu_init(void)
return 0;
}
#endif
void board_debug_uart_init(void)
{

3
arch/arm/mach-rockchip/rv1126/rv1126.c
View File

@ -536,6 +536,7 @@ void board_debug_uart_init(void)
#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
}
#ifndef CONFIG_TPL_BUILD
int arch_cpu_init(void)
{
/*
@ -688,9 +689,9 @@ int arch_cpu_init(void)
/* GPIO0_D6 pull down in default, pull up it for SPI Flash */
writel(((0x3 << 12) << 16) | (0x1 << 12), GRF1_GPIO0D_P);
#endif
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
int spl_fit_standalone_release(uintptr_t entry_point)

6
arch/arm/mach-rockchip/tpl.c
View File

@ -114,6 +114,11 @@ __weak void rockchip_stimer_init(void)
writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
}
__weak int arch_cpu_init(void)
{
return 0;
}
void board_init_f(ulong dummy)
{
#if defined(CONFIG_SPL_FRAMEWORK) && !CONFIG_IS_ENABLED(TINY_FRAMEWORK)
@ -122,6 +127,7 @@ void board_init_f(ulong dummy)
#endif
rockchip_stimer_init();
arch_cpu_init();
#define EARLY_DEBUG
#ifdef EARLY_DEBUG
/*