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clk: rockchip: rk3368: print arm enter and init rate 

Change-Id: Ib201cf442ce7398bbe8009ce9b7de9dc1f53c587
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-01-22 16:26:41 +08:00 committed by Jianhong Chen
parent 08e6e2645e
commit ae79bf6827
2 changed files with 46 additions and 8 deletions
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8
arch/arm/include/asm/arch-rockchip/cru_rk3368.h
View File

@ -57,6 +57,14 @@ check_member(rk3368_cru, emmc_con[1], 0x41c);
struct rk3368_clk_priv {
struct rk3368_cru *cru;
ulong armlclk_hz;
ulong armlclk_enter_hz;
ulong armlclk_init_hz;
ulong armbclk_hz;
ulong armbclk_enter_hz;
ulong armbclk_init_hz;
bool sync_kernel;
bool set_armclk_rate;
};
enum {

46
drivers/clk/rockchip/clk_rk3368.c
View File

@ -920,8 +920,14 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
ret = rkclk_set_pll(priv->cru, clk->id - 1, &pll_config);
break;
case ARMCLKB:
if (priv->armbclk_hz)
ret = rk3368_armclk_set_clk(priv, clk->id, rate);
priv->armbclk_hz = rate;
break;
case ARMCLKL:
ret = rk3368_armclk_set_clk(priv, clk->id, rate);
if (priv->armlclk_hz)
ret = rk3368_armclk_set_clk(priv, clk->id, rate);
priv->armlclk_hz = rate;
break;
case SCLK_SPI0 ... SCLK_SPI2:
ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
@ -1195,13 +1201,24 @@ static int rk3368_clk_probe(struct udevice *dev)
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
priv->sync_kernel = false;
if (!priv->armlclk_enter_hz)
priv->armlclk_enter_hz = rkclk_pll_get_rate(priv->cru, APLLL);
if (!priv->armbclk_enter_hz)
priv->armbclk_enter_hz = rkclk_pll_get_rate(priv->cru, APLLB);
#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
rkclk_init(priv->cru);
#endif
if (!priv->armlclk_init_hz)
priv->armlclk_init_hz = rkclk_pll_get_rate(priv->cru, APLLL);
if (!priv->armbclk_init_hz)
priv->armbclk_init_hz = rkclk_pll_get_rate(priv->cru, APLLB);
/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
ret = clk_set_defaults(dev);
if (ret)
debug("%s clk_set_defaults failed %d\n", __func__, ret);
else
priv->sync_kernel = true;
return 0;
}
@ -1281,6 +1298,7 @@ U_BOOT_DRIVER(rockchip_rk3368_cru) = {
int soc_clk_dump(void)
{
struct udevice *cru_dev;
struct rk3368_clk_priv *priv;
const struct rk3368_clk_info *clk_dump;
struct clk clk;
unsigned long clk_count = ARRAY_SIZE(clks_dump);
@ -1295,7 +1313,19 @@ int soc_clk_dump(void)
return ret;
}
printf("CLK:");
priv = dev_get_priv(cru_dev);
printf("CLK: (%s. arml: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
priv->sync_kernel ? "sync kernel" : "uboot",
priv->armlclk_enter_hz / 1000,
priv->armlclk_init_hz / 1000,
priv->set_armclk_rate ? priv->armlclk_hz / 1000 : 0,
priv->set_armclk_rate ? " KHz" : "N/A");
printf("CLK: (%s. armb: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
priv->sync_kernel ? "sync kernel" : "uboot",
priv->armbclk_enter_hz / 1000,
priv->armbclk_init_hz / 1000,
priv->set_armclk_rate ? priv->armlclk_hz / 1000 : 0,
priv->set_armclk_rate ? " KHz" : "N/A");
for (i = 0; i < clk_count; i++) {
clk_dump = &clks_dump[i];
if (clk_dump->name) {
@ -1309,18 +1339,18 @@ int soc_clk_dump(void)
clk_free(&clk);
if (i == 0) {
if (rate < 0)
printf("%10s%20s\n", clk_dump->name,
printf(" %s %s\n", clk_dump->name,
"unknown");
else
printf("%10s%20lu Hz\n", clk_dump->name,
rate);
printf(" %s %lu KHz\n", clk_dump->name,
rate / 1000);
} else {
if (rate < 0)
printf("%14s%20s\n", clk_dump->name,
printf(" %s %s\n", clk_dump->name,
"unknown");
else
printf("%14s%20lu Hz\n", clk_dump->name,
rate);
printf(" %s %lu KHz\n", clk_dump->name,
rate / 1000);
}
}
}