From aec089f883cea0b7dcffe814d4bee6273b30391e Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 11 Sep 2020 15:06:20 +0800 Subject: [PATCH] rockchip: rv1126: Pull up SFC IO2 GPIO0_D6 pull down in default, but it's needed for SPI Flash with WP# pin pull up. Change-Id: I80a79e0072f1fff49673bbe834f51603e10283dc Signed-off-by: Jon Lin --- arch/arm/mach-rockchip/rv1126/rv1126.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index 4b2e442edf..00599c74ca 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -72,6 +72,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CRU_SOFTRST_CON11 0xFF49032C #define PMUGRF_SOC_CON1 0xFE020104 #define GRF_IOFUNC_CON3 0xFF01026C +#define GRF1_GPIO0D_P 0xFE010104 enum { GPIO1A7_SHIFT = 12, @@ -603,6 +604,10 @@ int arch_cpu_init(void) /* hold pmugrf's io reset */ writel(0x1 << 7 | 1 << 23, PMUGRF_SOC_CON1); #endif +#if defined(CONFIG_ROCKCHIP_SFC) && (defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)) + /* GPIO0_D6 pull down in default, pull up it for SPI Flash */ + writel(((0x3 << 12) << 16) | (0x1 << 12), GRF1_GPIO0D_P); +#endif return 0; }