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rockchip: rv1126: Pull up SFC IO2 

GPIO0_D6 pull down in default, but it's needed for SPI Flash with
WP# pin pull up.

Change-Id: I80a79e0072f1fff49673bbe834f51603e10283dc
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin 2020-09-11 15:06:20 +08:00
parent 1dd64bce5e
commit aec089f883
1 changed files with 5 additions and 0 deletions
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5
arch/arm/mach-rockchip/rv1126/rv1126.c
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@ -72,6 +72,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define CRU_SOFTRST_CON11 0xFF49032C #define CRU_SOFTRST_CON11 0xFF49032C
#define PMUGRF_SOC_CON1 0xFE020104 #define PMUGRF_SOC_CON1 0xFE020104
#define GRF_IOFUNC_CON3 0xFF01026C #define GRF_IOFUNC_CON3 0xFF01026C
#define GRF1_GPIO0D_P 0xFE010104
enum { enum {
GPIO1A7_SHIFT = 12, GPIO1A7_SHIFT = 12,
@ -603,6 +604,10 @@ int arch_cpu_init(void)
/* hold pmugrf's io reset */ /* hold pmugrf's io reset */
writel(0x1 << 7 | 1 << 23, PMUGRF_SOC_CON1); writel(0x1 << 7 | 1 << 23, PMUGRF_SOC_CON1);
#endif #endif
#if defined(CONFIG_ROCKCHIP_SFC) && (defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG))
/* GPIO0_D6 pull down in default, pull up it for SPI Flash */
writel(((0x3 << 12) << 16) | (0x1 << 12), GRF1_GPIO0D_P);
#endif
return 0; return 0;
} }