edid: support decode edid to drm modes
Change-Id: I38f82586d81177a4e6f5c20815af5480b40d2ff8 Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This commit is contained in:
Mark Yao
Kever Yang
parent
d807358c86
commit
b9e63a962a
106
common/edid.c
106
common/edid.c
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@ -16,6 +16,7 @@
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#include <fdtdec.h>
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#include <linux/ctype.h>
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#include <linux/string.h>
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#include <drm_modes.h>
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int edid_check_info(struct edid1_info *edid_info)
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{
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@ -136,6 +137,62 @@ static void decode_timing(u8 *buf, struct display_timing *timing)
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va + vbl, vborder);
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}
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/**
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* decode_mode() - Decoding an 18-byte detailed timing record
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*
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* @buf: Pointer to EDID detailed timing record
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* @timing: Place to put timing
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*/
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static void decode_mode(u8 *buf, struct drm_display_mode *mode)
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{
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uint x_mm, y_mm;
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unsigned int ha, hbl, hso, hspw, hborder;
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unsigned int va, vbl, vso, vspw, vborder;
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struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf;
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x_mm = (buf[12] + ((buf[14] & 0xf0) << 4));
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y_mm = (buf[13] + ((buf[14] & 0x0f) << 8));
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ha = (buf[2] + ((buf[4] & 0xf0) << 4));
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hbl = (buf[3] + ((buf[4] & 0x0f) << 8));
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hso = (buf[8] + ((buf[11] & 0xc0) << 2));
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hspw = (buf[9] + ((buf[11] & 0x30) << 4));
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hborder = buf[15];
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va = (buf[5] + ((buf[7] & 0xf0) << 4));
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vbl = (buf[6] + ((buf[7] & 0x0f) << 8));
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vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2));
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vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4));
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vborder = buf[16];
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/* Edid contains pixel clock in terms of 10KHz */
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mode->clock = (buf[0] + (buf[1] << 8)) * 10;
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mode->hdisplay = ha;
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mode->hsync_start = ha + hso;
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mode->hsync_end = ha + hso + hspw;
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mode->htotal = ha + hbl;
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mode->vdisplay = va;
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mode->vsync_start = va + vso;
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mode->vsync_end = va + vso + vspw;
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mode->vtotal = va + vbl;
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mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ?
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DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
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mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ?
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DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
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if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t))
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mode->flags |= DRM_MODE_FLAG_INTERLACE;
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debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n"
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" %04d %04d %04d %04d hborder %d\n"
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" %04d %04d %04d %04d vborder %d\n",
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mode->clock,
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x_mm, y_mm, mode->flags,
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mode->hdisplay, mode->hsync_start, mode->hsync_end,
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mode->htotal, hborder,
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mode->vdisplay, mode->vsync_start, mode->vsync_end,
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mode->vtotal, vborder);
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}
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/**
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* Check if HDMI vendor specific data block is present in CEA block
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* @param info CEA extension block
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@ -169,6 +226,54 @@ static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info)
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return false;
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}
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int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode,
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int *panel_bits_per_colourp)
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{
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struct edid1_info *edid = (struct edid1_info *)buf;
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bool timing_done;
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int i;
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if (buf_size < sizeof(*edid) || edid_check_info(edid)) {
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debug("%s: Invalid buffer\n", __func__);
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return -EINVAL;
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}
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if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) {
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debug("%s: No preferred timing\n", __func__);
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return -ENOENT;
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}
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/* Look for detailed timing */
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timing_done = false;
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for (i = 0; i < 4; i++) {
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struct edid_monitor_descriptor *desc;
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desc = &edid->monitor_details.descriptor[i];
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if (desc->zero_flag_1 != 0) {
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decode_mode((u8 *)desc, mode);
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timing_done = true;
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break;
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}
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}
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if (!timing_done)
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return -EINVAL;
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if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) {
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debug("%s: Not a digital display\n", __func__);
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return -ENOSYS;
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}
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if (edid->version != 1 || edid->revision < 4) {
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debug("%s: EDID version %d.%d does not have required info\n",
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__func__, edid->version, edid->revision);
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*panel_bits_per_colourp = -1;
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} else {
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*panel_bits_per_colourp =
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((edid->video_input_definition & 0x70) >> 3) + 4;
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}
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return 0;
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}
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int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing,
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int *panel_bits_per_colourp)
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{
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@ -226,6 +331,7 @@ int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing,
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return 0;
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}
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/**
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* Snip the tailing whitespace/return of a string.
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*
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@ -0,0 +1,67 @@
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/*
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* (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DRM_MODES_H
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#define _DRM_MODES_H
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/* Video mode flags */
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/* bit compatible with the xorg definitions. */
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#define DRM_MODE_FLAG_PHSYNC (1 << 0)
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#define DRM_MODE_FLAG_NHSYNC (1 << 1)
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#define DRM_MODE_FLAG_PVSYNC (1 << 2)
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#define DRM_MODE_FLAG_NVSYNC (1 << 3)
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#define DRM_MODE_FLAG_INTERLACE (1 << 4)
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#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
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#define DRM_MODE_FLAG_CSYNC (1 << 6)
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#define DRM_MODE_FLAG_PCSYNC (1 << 7)
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#define DRM_MODE_FLAG_NCSYNC (1 << 8)
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#define DRM_MODE_FLAG_HSKEW (1 << 9) /* hskew provided */
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#define DRM_MODE_FLAG_BCAST (1 << 10)
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#define DRM_MODE_FLAG_PIXMUX (1 << 11)
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#define DRM_MODE_FLAG_DBLCLK (1 << 12)
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#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
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#define DRM_MODE_CONNECTOR_Unknown 0
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#define DRM_MODE_CONNECTOR_VGA 1
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#define DRM_MODE_CONNECTOR_DVII 2
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#define DRM_MODE_CONNECTOR_DVID 3
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#define DRM_MODE_CONNECTOR_DVIA 4
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#define DRM_MODE_CONNECTOR_Composite 5
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#define DRM_MODE_CONNECTOR_SVIDEO 6
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#define DRM_MODE_CONNECTOR_LVDS 7
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#define DRM_MODE_CONNECTOR_Component 8
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#define DRM_MODE_CONNECTOR_9PinDIN 9
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#define DRM_MODE_CONNECTOR_DisplayPort 10
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#define DRM_MODE_CONNECTOR_HDMIA 11
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#define DRM_MODE_CONNECTOR_HDMIB 12
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#define DRM_MODE_CONNECTOR_TV 13
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#define DRM_MODE_CONNECTOR_eDP 14
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#define DRM_MODE_CONNECTOR_VIRTUAL 15
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#define DRM_MODE_CONNECTOR_DSI 16
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#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
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#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
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#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
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#define DRM_EDID_PT_STEREO (1 << 5)
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#define DRM_EDID_PT_INTERLACED (1 << 7)
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struct drm_display_mode {
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/* Proposed mode values */
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int clock; /* in kHz */
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int hdisplay;
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int hsync_start;
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int hsync_end;
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int htotal;
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int vdisplay;
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int vsync_start;
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int vsync_end;
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int vtotal;
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int vrefresh;
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int vscan;
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unsigned int flags;
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};
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#endif
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@ -305,6 +305,7 @@ int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin,
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unsigned int *hmax, unsigned int *vmin,
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unsigned int *vmax);
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struct drm_display_mode;
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struct display_timing;
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/**
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@ -320,5 +321,7 @@ struct display_timing;
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*/
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int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing,
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int *panel_bits_per_colourp);
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int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode,
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int *panel_bits_per_colourp);
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#endif /* __EDID_H_ */
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