rockchip: rk3036: use commong board file
Move some soc spec setting into rk3036.c Change-Id: Ib0c1d222e273e8a8bfc8c58d2e060b696f2a7500 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Kever Yang
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afb735a686
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ba59d97fad
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@ -1,104 +0,0 @@
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/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/grf_rk3036.h>
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#include <asm/arch/boot_mode.h>
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#include <asm/arch/sdram_rk3036.h>
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#include <asm/gpio.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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__weak int rk_board_late_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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setup_boot_mode();
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return rk_board_late_init();
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}
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int board_init(void)
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{
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return 0;
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}
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#if !CONFIG_IS_ENABLED(RAM)
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/*
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* When CONFIG_RAM is enabled, the dram_init() function is implemented
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* in sdram_common.c.
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*/
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int dram_init(void)
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{
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gd->ram_size = sdram_size();
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return 0;
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}
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
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#include <usb.h>
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#include <usb/dwc2_udc.h>
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static struct dwc2_plat_otg_data rk3036_otg_data = {
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.rx_fifo_sz = 512,
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.np_tx_fifo_sz = 16,
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.tx_fifo_sz = 128,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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int node;
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const char *mode;
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bool matched = false;
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const void *blob = gd->fdt_blob;
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/* find the usb_otg node */
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node = fdt_node_offset_by_compatible(blob, -1,
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"rockchip,rk3288-usb");
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while (node > 0) {
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mode = fdt_getprop(blob, node, "dr_mode", NULL);
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if (mode && strcmp(mode, "otg") == 0) {
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matched = true;
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break;
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}
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node = fdt_node_offset_by_compatible(blob, node,
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"rockchip,rk3288-usb");
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}
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if (!matched) {
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debug("Not found usb_otg device\n");
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return -ENODEV;
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}
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rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
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return dwc2_udc_probe(&rk3036_otg_data);
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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return 0;
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}
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#endif
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@ -4,7 +4,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += clk_rk3036.o
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obj-y += rk3036.o clk_rk3036.o
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ifndef CONFIG_SPL_BUILD
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obj-y += syscon_rk3036.o
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@ -1,28 +1,22 @@
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/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd
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* Copyright (c) 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <asm/io.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/grf_rk3036.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sdram_rk3036.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/uart.h>
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DECLARE_GLOBAL_DATA_PTR;
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#include <asm/arch/grf_rk3036.h>
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#define GRF_BASE 0x20008000
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#define DEBUG_UART_BASE 0x20068000
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void board_init_f(ulong dummy)
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#ifdef CONFIG_SPL_BUILD
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int arch_cpu_init(void)
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{
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return 0;
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}
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#endif
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void board_debug_uart_init(void)
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{
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#ifdef EARLY_DEBUG
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struct rk3036_grf * const grf = (void *)GRF_BASE;
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/*
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* NOTE: sd card and debug uart use same iomux in rk3036,
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@ -34,22 +28,5 @@ void board_init_f(ulong dummy)
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GPIO1C2_MASK << GPIO1C2_SHIFT,
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GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
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GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
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debug_uart_init();
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#endif
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rockchip_timer_init();
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sdram_init();
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/* return to maskrom */
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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}
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/* Place Holders */
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void board_init_r(gd_t *id, ulong dest_addr)
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{
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/*
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* Function attribute is no-return
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* This Function never executes
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*/
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while (1)
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;
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}
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@ -11,6 +11,7 @@
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#include <asm/arch/hardware.h>
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#include <asm/arch/sdram_rk3036.h>
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#include <asm/arch/uart.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* we can not fit the code to access the device tree in SPL
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@ -763,3 +764,16 @@ void sdram_init(void)
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move_to_access_state(&sdram_priv);
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dram_cfg_rbc(&sdram_priv);
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}
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#if !CONFIG_IS_ENABLED(RAM)
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/*
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* When CONFIG_RAM is enabled, the dram_init() function is implemented
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* in sdram_common.c.
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*/
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int dram_init(void)
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{
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gd->ram_size = sdram_size();
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return 0;
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}
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#endif
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