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clk: rockchip: rk312x: add cpll freq init 

Add cpll freq setting in rkclk_init.
If have vop display, the cpll is just for dclk vop.
The cpll freq will be setting by dclk freq set.
But if no vop display, the cpll need to set init freq for other
children clk.

Change-Id: Ia45892dd3c8efb77cf32b631329d927aceb8dd86
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-09-28 17:03:59 +08:00 committed by Kever Yang
parent 5ef8980810
commit ba5feded0a
2 changed files with 5 additions and 0 deletions
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1
arch/arm/include/asm/arch-rockchip/cru_rk3128.h
View File

@ -14,6 +14,7 @@
#define APLL_HZ (600 * MHz)
#define GPLL_HZ (594 * MHz)
#define CPLL_HZ (400 * MHz)
#define ACLK_BUS_HZ (148500000)
#define ACLK_PERI_HZ (148500000)

4
drivers/clk/rockchip/clk_rk3128.c
View File

@ -43,6 +43,7 @@ static struct rockchip_pll_rate_table rk3128_pll_rates[] = {
RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
RK3036_PLL_RATE(400000000, 1, 100, 6, 1, 1, 0),
{ /* sentinel */ },
};
@ -756,6 +757,9 @@ static void rkclk_init(struct rk3128_clk_priv *priv)
rk3128_peri_set_clk(priv, ACLK_PERI, ACLK_PERI_HZ);
rk3128_peri_set_clk(priv, HCLK_PERI, ACLK_PERI_HZ / 2);
rk3128_peri_set_clk(priv, PCLK_PERI, ACLK_PERI_HZ / 2);
rockchip_pll_set_rate(&rk3128_pll_clks[CPLL],
priv->cru, CPLL, CPLL_HZ);
}
static int rk3128_clk_probe(struct udevice *dev)