video/bridge: anx6345: Convert to rockchip_bridge
Use the rockchip_bridge_funcs instead of the video_bridge_ops so that anx6345 device can work on the rockchip platform. Change-Id: I3ded401816ba8347bddfedcae8aacab4667df2af Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
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@ -83,6 +83,7 @@
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#define ANX9804_VID_CTRL1_REG 0x08
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#define ANX9804_VID_CTRL1_REG 0x08
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#define ANX9804_VID_CTRL1_VID_EN BIT(7)
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#define ANX9804_VID_CTRL1_VID_EN BIT(7)
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#define ANX9804_VID_CTRL1_DDR_CTRL BIT(1)
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#define ANX9804_VID_CTRL1_EDGE BIT(0)
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#define ANX9804_VID_CTRL1_EDGE BIT(0)
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#define ANX9804_VID_CTRL2_REG 0x09
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#define ANX9804_VID_CTRL2_REG 0x09
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@ -11,6 +11,7 @@
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#include <edid.h>
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#include <edid.h>
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#include <video_bridge.h>
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#include <video_bridge.h>
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#include "../anx98xx-edp.h"
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#include "../anx98xx-edp.h"
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#include "../drm/rockchip_bridge.h"
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#define DP_MAX_LINK_RATE 0x001
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#define DP_MAX_LINK_RATE 0x001
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#define DP_MAX_LANE_COUNT 0x002
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#define DP_MAX_LANE_COUNT 0x002
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@ -19,6 +20,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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struct anx6345_priv {
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struct anx6345_priv {
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u8 chipid;
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u8 edid[EDID_SIZE];
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u8 edid[EDID_SIZE];
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};
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};
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@ -254,6 +256,13 @@ static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)
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static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
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static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
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{
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{
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struct anx6345_priv *priv = dev_get_priv(dev);
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struct anx6345_priv *priv = dev_get_priv(dev);
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int ret;
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ret = anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
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if (ret < 0) {
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dev_err(dev, "failed to get edid\n");
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return ret;
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}
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if (size > EDID_SIZE)
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if (size > EDID_SIZE)
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size = EDID_SIZE;
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size = EDID_SIZE;
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@ -268,12 +277,11 @@ static int anx6345_attach(struct udevice *dev)
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return 0;
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return 0;
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}
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}
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static int anx6345_enable(struct udevice *dev)
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static int anx6345_init(struct udevice *dev)
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{
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{
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u8 chipid, colordepth, lanes, data_rate, c;
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int ret, i, bpp;
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struct display_timing timing;
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struct anx6345_priv *priv = dev_get_priv(dev);
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struct anx6345_priv *priv = dev_get_priv(dev);
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u8 c;
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int ret, i;
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/* Deassert reset and enable power */
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/* Deassert reset and enable power */
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ret = video_bridge_set_active(dev, true);
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ret = video_bridge_set_active(dev, true);
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@ -288,16 +296,16 @@ static int anx6345_enable(struct udevice *dev)
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/* Write 0 to the powerdown reg (powerup everything) */
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/* Write 0 to the powerdown reg (powerup everything) */
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anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
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anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
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ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid);
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ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &priv->chipid);
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if (ret)
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if (ret)
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debug("%s: read id failed: %d\n", __func__, ret);
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debug("%s: read id failed: %d\n", __func__, ret);
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switch (chipid) {
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switch (priv->chipid) {
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case 0x63:
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case 0x63:
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debug("ANX63xx detected.\n");
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debug("ANX63xx detected.\n");
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break;
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break;
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default:
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default:
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debug("Error anx6345 chipid mismatch: %.2x\n", (int)chipid);
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debug("Error anx6345 chipid mismatch: %.2x\n", priv->chipid);
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return -ENODEV;
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return -ENODEV;
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}
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}
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@ -339,7 +347,16 @@ static int anx6345_enable(struct udevice *dev)
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anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
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anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
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anx6345_write_r0(dev, 0xa7, 0x00);
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anx6345_write_r0(dev, 0xa7, 0x00);
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anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
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return 0;
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}
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static int anx6345_enable(struct udevice *dev)
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{
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u8 colordepth, lanes, data_rate, c;
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int i, bpp;
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struct display_timing timing;
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struct anx6345_priv *priv = dev_get_priv(dev);
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if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
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if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
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debug("Failed to parse EDID\n");
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debug("Failed to parse EDID\n");
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return -EIO;
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return -EIO;
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@ -374,7 +391,7 @@ static int anx6345_enable(struct udevice *dev)
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mdelay(5);
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mdelay(5);
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for (i = 0; i < 100; i++) {
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for (i = 0; i < 100; i++) {
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anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
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anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
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if ((chipid == 0x63) && (c & 0x80) == 0)
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if ((priv->chipid == 0x63) && (c & 0x80) == 0)
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break;
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break;
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mdelay(5);
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mdelay(5);
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@ -385,8 +402,8 @@ static int anx6345_enable(struct udevice *dev)
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}
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}
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/* Enable */
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/* Enable */
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anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG,
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anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG, ANX9804_VID_CTRL1_VID_EN |
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ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
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ANX9804_VID_CTRL1_DDR_CTRL | ANX9804_VID_CTRL1_EDGE);
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/* Force stream valid */
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/* Force stream valid */
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anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
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anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
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ANX9804_SYS_CTRL3_F_HPD |
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ANX9804_SYS_CTRL3_F_HPD |
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@ -399,20 +416,40 @@ static int anx6345_enable(struct udevice *dev)
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static int anx6345_probe(struct udevice *dev)
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static int anx6345_probe(struct udevice *dev)
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{
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{
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struct rockchip_bridge *bridge =
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(struct rockchip_bridge *)dev_get_driver_data(dev);
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if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
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if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
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return -EPROTONOSUPPORT;
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return -EPROTONOSUPPORT;
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return anx6345_enable(dev);
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bridge->dev = dev;
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return anx6345_init(dev);
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}
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}
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struct video_bridge_ops anx6345_ops = {
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static const struct video_bridge_ops anx6345_ops = {
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.attach = anx6345_attach,
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.attach = anx6345_attach,
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.set_backlight = anx6345_set_backlight,
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.set_backlight = anx6345_set_backlight,
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.read_edid = anx6345_read_edid,
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.read_edid = anx6345_read_edid,
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};
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};
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static void anx6345_bridge_enable(struct rockchip_bridge *bridge)
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{
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anx6345_enable(bridge->dev);
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}
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static const struct rockchip_bridge_funcs anx6345_bridge_funcs = {
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.enable = anx6345_bridge_enable,
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};
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static struct rockchip_bridge anx6345_driver_data = {
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.funcs = &anx6345_bridge_funcs,
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};
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static const struct udevice_id anx6345_ids[] = {
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static const struct udevice_id anx6345_ids[] = {
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{ .compatible = "analogix,anx6345", },
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{
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.compatible = "analogix,anx6345",
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.data = (ulong)&anx6345_driver_data, },
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{ }
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{ }
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};
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};
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