video/bridge: anx6345: Convert to rockchip_bridge

Use the rockchip_bridge_funcs instead of the video_bridge_ops so that
anx6345 device can work on the rockchip platform.

Change-Id: I3ded401816ba8347bddfedcae8aacab4667df2af
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi 2018-12-17 20:29:11 +08:00
parent a4878dda5e
commit c52351ffbe
2 changed files with 52 additions and 14 deletions

View File

@ -83,6 +83,7 @@
#define ANX9804_VID_CTRL1_REG 0x08 #define ANX9804_VID_CTRL1_REG 0x08
#define ANX9804_VID_CTRL1_VID_EN BIT(7) #define ANX9804_VID_CTRL1_VID_EN BIT(7)
#define ANX9804_VID_CTRL1_DDR_CTRL BIT(1)
#define ANX9804_VID_CTRL1_EDGE BIT(0) #define ANX9804_VID_CTRL1_EDGE BIT(0)
#define ANX9804_VID_CTRL2_REG 0x09 #define ANX9804_VID_CTRL2_REG 0x09

View File

@ -11,6 +11,7 @@
#include <edid.h> #include <edid.h>
#include <video_bridge.h> #include <video_bridge.h>
#include "../anx98xx-edp.h" #include "../anx98xx-edp.h"
#include "../drm/rockchip_bridge.h"
#define DP_MAX_LINK_RATE 0x001 #define DP_MAX_LINK_RATE 0x001
#define DP_MAX_LANE_COUNT 0x002 #define DP_MAX_LANE_COUNT 0x002
@ -19,6 +20,7 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
struct anx6345_priv { struct anx6345_priv {
u8 chipid;
u8 edid[EDID_SIZE]; u8 edid[EDID_SIZE];
}; };
@ -254,6 +256,13 @@ static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)
static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size) static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
{ {
struct anx6345_priv *priv = dev_get_priv(dev); struct anx6345_priv *priv = dev_get_priv(dev);
int ret;
ret = anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
if (ret < 0) {
dev_err(dev, "failed to get edid\n");
return ret;
}
if (size > EDID_SIZE) if (size > EDID_SIZE)
size = EDID_SIZE; size = EDID_SIZE;
@ -268,12 +277,11 @@ static int anx6345_attach(struct udevice *dev)
return 0; return 0;
} }
static int anx6345_enable(struct udevice *dev) static int anx6345_init(struct udevice *dev)
{ {
u8 chipid, colordepth, lanes, data_rate, c;
int ret, i, bpp;
struct display_timing timing;
struct anx6345_priv *priv = dev_get_priv(dev); struct anx6345_priv *priv = dev_get_priv(dev);
u8 c;
int ret, i;
/* Deassert reset and enable power */ /* Deassert reset and enable power */
ret = video_bridge_set_active(dev, true); ret = video_bridge_set_active(dev, true);
@ -288,16 +296,16 @@ static int anx6345_enable(struct udevice *dev)
/* Write 0 to the powerdown reg (powerup everything) */ /* Write 0 to the powerdown reg (powerup everything) */
anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0); anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid); ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &priv->chipid);
if (ret) if (ret)
debug("%s: read id failed: %d\n", __func__, ret); debug("%s: read id failed: %d\n", __func__, ret);
switch (chipid) { switch (priv->chipid) {
case 0x63: case 0x63:
debug("ANX63xx detected.\n"); debug("ANX63xx detected.\n");
break; break;
default: default:
debug("Error anx6345 chipid mismatch: %.2x\n", (int)chipid); debug("Error anx6345 chipid mismatch: %.2x\n", priv->chipid);
return -ENODEV; return -ENODEV;
} }
@ -339,7 +347,16 @@ static int anx6345_enable(struct udevice *dev)
anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00); anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
anx6345_write_r0(dev, 0xa7, 0x00); anx6345_write_r0(dev, 0xa7, 0x00);
anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid); return 0;
}
static int anx6345_enable(struct udevice *dev)
{
u8 colordepth, lanes, data_rate, c;
int i, bpp;
struct display_timing timing;
struct anx6345_priv *priv = dev_get_priv(dev);
if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) { if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
debug("Failed to parse EDID\n"); debug("Failed to parse EDID\n");
return -EIO; return -EIO;
@ -374,7 +391,7 @@ static int anx6345_enable(struct udevice *dev)
mdelay(5); mdelay(5);
for (i = 0; i < 100; i++) { for (i = 0; i < 100; i++) {
anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c); anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
if ((chipid == 0x63) && (c & 0x80) == 0) if ((priv->chipid == 0x63) && (c & 0x80) == 0)
break; break;
mdelay(5); mdelay(5);
@ -385,8 +402,8 @@ static int anx6345_enable(struct udevice *dev)
} }
/* Enable */ /* Enable */
anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG, anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG, ANX9804_VID_CTRL1_VID_EN |
ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE); ANX9804_VID_CTRL1_DDR_CTRL | ANX9804_VID_CTRL1_EDGE);
/* Force stream valid */ /* Force stream valid */
anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG, anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_F_HPD |
@ -399,20 +416,40 @@ static int anx6345_enable(struct udevice *dev)
static int anx6345_probe(struct udevice *dev) static int anx6345_probe(struct udevice *dev)
{ {
struct rockchip_bridge *bridge =
(struct rockchip_bridge *)dev_get_driver_data(dev);
if (device_get_uclass_id(dev->parent) != UCLASS_I2C) if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
return -EPROTONOSUPPORT; return -EPROTONOSUPPORT;
return anx6345_enable(dev); bridge->dev = dev;
return anx6345_init(dev);
} }
struct video_bridge_ops anx6345_ops = { static const struct video_bridge_ops anx6345_ops = {
.attach = anx6345_attach, .attach = anx6345_attach,
.set_backlight = anx6345_set_backlight, .set_backlight = anx6345_set_backlight,
.read_edid = anx6345_read_edid, .read_edid = anx6345_read_edid,
}; };
static void anx6345_bridge_enable(struct rockchip_bridge *bridge)
{
anx6345_enable(bridge->dev);
}
static const struct rockchip_bridge_funcs anx6345_bridge_funcs = {
.enable = anx6345_bridge_enable,
};
static struct rockchip_bridge anx6345_driver_data = {
.funcs = &anx6345_bridge_funcs,
};
static const struct udevice_id anx6345_ids[] = { static const struct udevice_id anx6345_ids[] = {
{ .compatible = "analogix,anx6345", }, {
.compatible = "analogix,anx6345",
.data = (ulong)&anx6345_driver_data, },
{ } { }
}; };