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rockchip: clk: rk3399: fix up the hdmi clk error 

make the dclk_vop div=1.

Change-Id: I0faedbd557cddd55f93529d66f2f7815ce4c5f9e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-07-14 17:36:21 +08:00 committed by Kever Yang
parent c5c7b477df
commit c6c6283c78
1 changed files with 3 additions and 6 deletions
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9
drivers/clk/rockchip/clk_rk3399.c
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@ -696,7 +696,6 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
return rk3399_spi_get_clk(cru, clk_id);
}
#define RK3399_LIMIT_PLL_DCLK_VOP (600 * 1000000)
#define RK3399_LIMIT_PLL_ACLK_VOP (400 * 1000000)
static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
@ -727,14 +726,12 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT |
(div - 1) << ACLK_VOP_DIV_CON_SHIFT);
div = DIV_ROUND_UP(RK3399_LIMIT_PLL_DCLK_VOP, hz);
if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) {
if (pll_para_config(div * hz, &cpll_config))
if (pll_para_config(hz, &cpll_config))
return -1;
rkclk_set_pll(&cru->cpll_con[0], &cpll_config);
} else {
if (pll_para_config(div * hz, &vpll_config))
if (pll_para_config(hz, &vpll_config))
return -1;
rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
}
@ -742,7 +739,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
rk_clrsetreg(dclkreg_addr,
DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_DIV_CON_MASK,
DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
(div - 1) << DCLK_VOP_DIV_CON_SHIFT);
(1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
return hz;
}