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UPSTREAM: rockchip: clk: rk3399: add clk_enable function and support USB HOST0/1 

The generic ehci-driver (ehci-generic.c) will try to enable the clocks
listed in the DTSI. If this fails (e.g. due to clk_enable not being
implemented in a driver and -ENOSYS being returned by the clk-uclass),
the driver will bail our and print an error message.

This implements a minimal clk_enable for the RK3399 and supports the
clocks mandatory for the EHCI controllers; as these are enabled by
default we simply return success.

Change-Id: Ic38cdb4e599c1fd8534b5e998b970b4610ab7383
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 2f01a2b2149c4c38467eeeddde09ac48d379aed3)
This commit is contained in:
Philipp Tomsich 2017-09-12 17:30:56 +02:00 committed by Kever Yang
parent 1dc5824468
commit cce8d7cd22
1 changed files with 15 additions and 0 deletions
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15
drivers/clk/rockchip/clk_rk3399.c
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@ -906,9 +906,24 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
return ret;
}
static int rk3399_clk_enable(struct clk *clk)
{
switch (clk->id) {
case HCLK_HOST0:
case HCLK_HOST0_ARB:
case HCLK_HOST1:
case HCLK_HOST1_ARB:
return 0;
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
return -ENOENT;
}
static struct clk_ops rk3399_clk_ops = {
.get_rate = rk3399_clk_get_rate,
.set_rate = rk3399_clk_set_rate,
.enable = rk3399_clk_enable,
};
#ifdef CONFIG_SPL_BUILD