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pinctrl/rockchip: add support for rv1126 

Change-Id: I177bbdf40d3becf848c054721f0986d7d3c6b1cd
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Jianqun Xu 2020-03-10 16:14:40 +08:00
parent 979aa338cb
commit cf04a17b62
1 changed files with 196 additions and 4 deletions
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200
drivers/pinctrl/pinctrl-rockchip.c
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@ -19,6 +19,7 @@
enum rockchip_pinctrl_type {
PX30,
RV1108,
RV1126,
RK1808,
RK2928,
RK3066B,
@ -40,6 +41,7 @@ enum rockchip_pinctrl_type {
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_8WIDTH_2BIT BIT(5)
#define IOMUX_WRITABLE_32BIT BIT(6)
#define IOMUX_L_SOURCE_PMU BIT(7)
/**
* @type: iomux variant using IOMUX_* constants
@ -422,6 +424,37 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
},
};
static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
{
.num = 0,
.pin = 20,
.reg = 0x10000,
.bit = 0,
.mask = 0xf
},
{
.num = 0,
.pin = 21,
.reg = 0x10000,
.bit = 4,
.mask = 0xf
},
{
.num = 0,
.pin = 22,
.reg = 0x10000,
.bit = 8,
.mask = 0xf
},
{
.num = 0,
.pin = 23,
.reg = 0x10000,
.bit = 12,
.mask = 0xf
},
};
static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
{
.num = 2,
@ -1411,8 +1444,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return RK_FUNC_GPIO;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
regmap = priv->regmap_pmu;
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
else
regmap = priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@ -1504,8 +1541,12 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
regmap = priv->regmap_pmu;
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
else
regmap = priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@ -1729,6 +1770,114 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RV1126_PULL_PMU_OFFSET 0x40
#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
#define RV1126_PULL_PINS_PER_REG 8
#define RV1126_PULL_BITS_PER_PIN 2
#define RV1126_PULL_BANK_STRIDE 16
#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = priv->regmap_base;
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
*bit = pin_num % RV1126_PULL_PINS_PER_REG;
*bit *= RV1126_PULL_BITS_PER_PIN;
return;
}
*regmap = priv->regmap_pmu;
*reg = RV1126_PULL_PMU_OFFSET;
} else {
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
*regmap = priv->regmap_base;
*reg += bank->bank_num * RV1126_PULL_BANK_STRIDE;
}
*reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
*bit *= RV1126_PULL_BITS_PER_PIN;
}
#define RV1126_DRV_PMU_OFFSET 0x20
#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
#define RV1126_DRV_BITS_PER_PIN 4
#define RV1126_DRV_PINS_PER_REG 4
#define RV1126_DRV_BANK_STRIDE 32
static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = priv->regmap_base;
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
*bit *= RV1126_DRV_BITS_PER_PIN;
return;
}
*regmap = priv->regmap_pmu;
*reg = RV1126_DRV_PMU_OFFSET;
} else {
*regmap = priv->regmap_base;
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
*reg += bank->bank_num * RV1126_DRV_BANK_STRIDE;
}
*reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
*bit *= RV1126_DRV_BITS_PER_PIN;
}
#define RV1126_SCHMITT_PMU_OFFSET 0x60
#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
#define RV1126_SCHMITT_BANK_STRIDE 16
#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int pins_per_reg;
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = priv->regmap_base;
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
*bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
return 0;
}
*regmap = priv->regmap_pmu;
*reg = RV1126_SCHMITT_PMU_OFFSET;
pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
} else {
*regmap = priv->regmap_base;
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
*reg += bank->bank_num * RV1126_SCHMITT_BANK_STRIDE;
}
*reg += ((pin_num / pins_per_reg) * 4);
*bit = pin_num % pins_per_reg;
return 0;
}
#define RK1808_PULL_PMU_OFFSET 0x10
#define RK1808_PULL_GRF_OFFSET 0x80
#define RK1808_PULL_PINS_PER_REG 8
@ -2296,6 +2445,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
break;
case PX30:
case RV1108:
case RV1126:
case RK1808:
case RK3188:
case RK3288:
@ -2453,6 +2603,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
return pull ? false : true;
case PX30:
case RV1108:
case RV1126:
case RK1808:
case RK3188:
case RK3288:
@ -2949,6 +3100,45 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rv1126_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
IOMUX_WIDTH_4BIT, 0, 0, 0),
};
static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
.pin_banks = rv1126_pin_banks,
.nr_banks = ARRAY_SIZE(rv1126_pin_banks),
.label = "RV1126-GPIO",
.type = RV1126,
.grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
.pmu_mux_offset = 0x0,
.iomux_recalced = rv1126_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
.pull_calc_reg = rv1126_calc_pull_reg_and_bit,
.drv_calc_reg = rv1126_calc_drv_reg_and_bit,
.schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk1808_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
IOMUX_SOURCE_PMU,
@ -3328,6 +3518,8 @@ static const struct udevice_id rockchip_pinctrl_dt_match[] = {
.data = (ulong)&px30_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = (ulong)&rv1108_pin_ctrl },
{ .compatible = "rockchip,rv1126-pinctrl",
.data = (ulong)&rv1126_pin_ctrl },
{ .compatible = "rockchip,rk1808-pinctrl",
.data = (ulong)&rk1808_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",